ATSAM3U4EA-CU Atmel, ATSAM3U4EA-CU Datasheet - Page 147

• Manufacturer Part Number: ATSAM3U4EA-CU
• Description: IC MCU 32BIT 256KB FLSH 144LFBGA
• Manufacturer: Atmel
• Series: SAM3Ur

Specifications of ATSAM3U4EA-CU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 96MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 52K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b, 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LFBGA
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 52 KB
• Interface Type: 4xUSART, 2xTWI, 5xSPI, Bus
• Maximum Clock Frequency: 96 MHz
• Number Of Programmable I/os: 96
• Number Of Timers: 8
• Operating Supply Voltage: 1.62 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-CM3, AT91SAM3U-EK, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3U-EK
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

13.16.1.4
13.16.1.5
6430D–ATARM–25-Mar-11
B
BLE
B.W
BEQ
BEQ.W
BL
BX
BXNE
BLX
Condition flags
Examples
loopA
ng
target ; Branch to target within 16MB range
target ; Conditionally branch to target
target ; Conditionally branch to target within 1MB
funC
LR
R0
R0
; Branch to loopA
; Conditionally branch to label ng
; Branch with link (Call) to function funC, return address
; stored in LR
; Return from function call
; Conditionally branch to address stored in R0
; Branch with link and exchange (Call) to a address stored
; in R0
Bcond is the only conditional instruction that is not required to be inside an IT block. However, it
has a longer branch range when it is inside an IT block.
These instructions do not change the flags.
• do not use PC in the BLX instruction
• for BX and BLX, bit[0] of Rm must be 1 for correct execution but a branch occurs to the target
• when any of these instructions is inside an IT block, it must be the last instruction of the IT
address created by changing bit[0] to 0
block.
SAM3U Series
147