ATSAM3U4EA-CU Atmel, ATSAM3U4EA-CU Datasheet - Page 814

• Manufacturer Part Number: ATSAM3U4EA-CU
• Description: IC MCU 32BIT 256KB FLSH 144LFBGA
• Manufacturer: Atmel
• Series: SAM3Ur

Specifications of ATSAM3U4EA-CU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 96MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 52K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b, 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LFBGA
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 52 KB
• Interface Type: 4xUSART, 2xTWI, 5xSPI, Bus
• Maximum Clock Frequency: 96 MHz
• Number Of Programmable I/os: 96
• Number Of Timers: 8
• Operating Supply Voltage: 1.62 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-CM3, AT91SAM3U-EK, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3U-EK
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

814
SAM3U Series
The following flowchart
tiple block transfers with the DMA Controller. Polling or interrupt method can be used to wait for
the end of write according to the contents of the Interrupt Mask Register (HSMCI_IMR).
Figure 37-10. Read Multiple Block and Write Multiple Block
Notes:
1. It is assumed that this command has been correctly sent (see
2. Handle errors reported in HSMCI_SR.
READ_MULTIPLE_BLOCK command (1)
Configure the HDMA channel X
DMAC_SADDRx and DMAC_DADDRx
DMAC_BTSIZE = BlockLength/4
(Figure
Read status register DMAC_EBCISR
Send SET_BLOCKLEN command
Send WRITE_MULTIPLE_BLOCK or
Send SELECT/DESELECT_CARD
Read status register HSMCI_SR
Set the block length
HSMCI_MR |= (BlockLength << 16)
Set the DMAEN bit
HSMCI_DMA |= DMAEN
command
Send STOP_TRANSMISSION
and Poll Bit FIFOEMPTY
DMAC_CHEN[X] = TRUE
and Poll Bit CBTC[X]
37-10) shows how to manage read multiple block and write mul-
New Buffer ? (2)
XFRDONE = 1
command (1)
(1)
RETURN
Poll the bit
to select the card
No
Yes
(1)
Yes
No
Figure
37-7).
6430D–ATARM–25-Mar-11