ATSAM3U4EA-CU Atmel, ATSAM3U4EA-CU Datasheet - Page 142

• Manufacturer Part Number: ATSAM3U4EA-CU
• Description: IC MCU 32BIT 256KB FLSH 144LFBGA
• Manufacturer: Atmel
• Series: SAM3Ur

Specifications of ATSAM3U4EA-CU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 96MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 52K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b, 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LFBGA
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 52 KB
• Interface Type: 4xUSART, 2xTWI, 5xSPI, Bus
• Maximum Clock Frequency: 96 MHz
• Number Of Programmable I/os: 96
• Number Of Timers: 8
• Operating Supply Voltage: 1.62 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-CM3, AT91SAM3U-EK, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3U-EK
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

13.15.1
13.15.1.1
13.15.1.2
13.15.1.3
13.15.1.4
13.15.1.5
142
BFC
BFI
SAM3U Series
BFC and BFI
Syntax
Operation
Restrictions
Condition flags
Examples
R4, #8, #12
R9, R2, #8, #12
Bit Field Clear and Bit Field Insert.
where:
cond
Rd
Rn
lsb
width
BFC clears a bitfield in a register. It clears width bits in Rd, starting at the low bit position lsb.
Other bits in Rd are unchanged.
BFI copies a bitfield into one register from another register. It replaces width bits in Rd starting at
the low bit position lsb, with width bits from Rn starting at bit[0]. Other bits in Rd are unchanged.
Do not use SP and do not use PC.
These instructions do not affect the flags.
BFC{cond} Rd, #lsb, #width
BFI{cond} Rd, Rn, #lsb, #width
; Clear bit 8 to bit 19 (12 bits) of R4 to 0
; Replace bit 8 to bit 19 (12 bits) of R9 with
; bit 0 to bit 11 from R2
is an optional condition code, see
is the destination register.
is the source register.
is the position of the least significant bit of the bitfield.
lsb must be in the range 0 to 31.
is the width of the bitfield and must be in the range 1 to 32− lsb.
“Conditional execution” on page
6430D–ATARM–25-Mar-11
100.