AT91SAM9XE512-CU Atmel, AT91SAM9XE512-CU Datasheet - Page 403

• Manufacturer Part Number: AT91SAM9XE512-CU
• Description: MCU ARM9 512K FLASH 217-BGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9XE512-CU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 180MHz
• Connectivity: EBI/EMI, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 56K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 217-LFBGA
• Package: 217LFBGA
• Device Core: ARM926EJ-S
• Family Name: 91S
• Maximum Speed: 180 MHz
• Operating Supply Voltage: 1.8|2.5|3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 96
• Interface Type: EBI/Ethernet/SPI/TWI/USART/USB
• On-chip Adc: 4-chx10-bit
• Number Of Timers: 6
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Ram Size: 32 KB
• Maximum Clock Frequency: 180 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, KSK-AT91SAM9XE-PL, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM9XE-EK
• Minimum Operating Temperature: - 40 C
• For Use With: AT91SAM9XE-EK - KIT EVAL FOR AT91SAM9XEAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Figure 31-4. Output Line Timings
31.4.8
31.4.9
6254C–ATARM–22-Jan-10
Write PIO_ODSR at 1
Write PIO_ODSR at 0
Write PIO_CODR
Write PIO_SODR
Inputs
Input Glitch Filtering
PIO_ODSR
PIO_PDSR
MCK
The level on each I/O line can be read through PIO_PDSR (Pin Data Status Register). This reg-
ister indicates the level of the I/O lines regardless of their configuration, whether uniquely as an
input or driven by the PIO controller or driven by a peripheral.
Reading the I/O line levels requires the clock of the PIO controller to be enabled, otherwise
PIO_PDSR reads the levels present on the I/O line at the time the clock was disabled.
Optional input glitch filters are independently programmable on each I/O line. When the glitch fil-
ter is enabled, a glitch with a duration of less than 1/2 Master Clock (MCK) cycle is automatically
rejected, while a pulse with a duration of 1 Master Clock cycle or more is accepted. For pulse
durations between 1/2 Master Clock cycle and 1 Master Clock cycle the pulse may or may not
be taken into account, depending on the precise timing of its occurrence. Thus for a pulse to be
visible it must exceed 1 Master Clock cycle, whereas for a glitch to be reliably filtered out, its
duration must not exceed 1/2 Master Clock cycle. The filter introduces one Master Clock cycle
latency if the pin level change occurs before a rising edge. However, this latency does not
appear if the pin level change occurs before a falling edge. This is illustrated in
The glitch filters are controlled by the register set; PIO_IFER (Input Filter Enable Register),
PIO_IFDR (Input Filter Disable Register) and PIO_IFSR (Input Filter Status Register). Writing
PIO_IFER and PIO_IFDR respectively sets and clears bits in PIO_IFSR. This last register
enables the glitch filter on the I/O lines.
When the glitch filter is enabled, it does not modify the behavior of the inputs on the peripherals.
It acts only on the value read in PIO_PDSR and on the input change interrupt detection. The
glitch filters require that the PIO Controller clock is enabled.
APB Access
AT91SAM9XE128/256/512 Preliminary
2 cycles
APB Access
2 cycles
Figure
31-5.
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