AT91SAM9XE512-CU Atmel, AT91SAM9XE512-CU Datasheet - Page 640

• Manufacturer Part Number: AT91SAM9XE512-CU
• Description: MCU ARM9 512K FLASH 217-BGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9XE512-CU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 180MHz
• Connectivity: EBI/EMI, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 56K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 217-LFBGA
• Package: 217LFBGA
• Device Core: ARM926EJ-S
• Family Name: 91S
• Maximum Speed: 180 MHz
• Operating Supply Voltage: 1.8|2.5|3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 96
• Interface Type: EBI/Ethernet/SPI/TWI/USART/USB
• On-chip Adc: 4-chx10-bit
• Number Of Timers: 6
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Ram Size: 32 KB
• Maximum Clock Frequency: 180 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, KSK-AT91SAM9XE-PL, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM9XE-EK
• Minimum Operating Temperature: - 40 C
• For Use With: AT91SAM9XE-EK - KIT EVAL FOR AT91SAM9XEAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

37.9.2
Name:
Address:
Access Type:
• CLKDIV: Clock Divider
Multimedia Card Interface clock (MCCK or MCI_CK) is Master Clock (MCK) divided by (2*(CLKDIV+1)).
• PWSDIV: Power Saving Divider
Multimedia Card Interface clock is divided by 2
Warning: This value must be different from 0 before enabling the Power Save Mode in the MCI_CR (MCI_PWSEN bit).
• RDPROOF Read Proof Enable
Enabling Read Proof allows to stop the MCI Clock during read access if the internal FIFO is full. This will guarantee data
integrity, not bandwidth.
0 = Disables Read Proof.
1 = Enables Read Proof.
• WRPROOF Write Proof Enable
Enabling Write Proof allows to stop the MCI Clock during write access if the internal FIFO is full. This will guarantee data
integrity, not bandwidth.
0 = Disables Write Proof.
1 = Enables Write Proof.
• PDCFBYTE: PDC Force Byte Transfer
Enabling PDC Force Byte Transfer allows the PDC to manage with internal byte transfers, so that transfer of blocks with a
size different from modulo 4 can be supported.
Warning: BLKLEN value depends on PDCFBYTE.
0 = Disables PDC Force Byte Transfer. PDC type of transfer are in words.
1 = Enables PDC Force Byte Transfer. PDC type of transfer are in bytes.
• PDCPADV: PDC Padding Value
0 = 0x00 value is used when padding data in write transfer (not only PDC transfer).
1 = 0xFF value is used when padding data in write transfer (not only PDC transfer).
6254C–ATARM–22-Jan-10
PDCMODE
31
23
15
7
MCI Mode Register
PDCPADV
30
22
14
MCI_MR
0xFFFA8004
Read/write
6
PDCFBYTE
29
21
13
5
(PWSDIV)
WRPROOF
AT91SAM9XE128/256/512 Preliminary
28
20
12
4
+ 1 when entering Power Saving Mode.
BLKLEN
BLKLEN
CLKDIV
RDPROOF
27
19
11
3
26
18
10
2
PWSDIV
25
17
9
1
24
16
8
0
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