ADUC7128BCPZ126 Analog Devices Inc, ADUC7128BCPZ126 Datasheet - Page 27

• Manufacturer Part Number: ADUC7128BCPZ126
• Description: IC DAS MCU ARM7 ADC/DDS 64-LFCSP
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7128BCPZ126

• Core Size: 16/32-Bit
• Program Memory Size: 126KB (126K x 8)
• Core Processor: ARM7
• Speed: 41.78MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: PLA, POR, PWM, PSM, Temp Sensor, WDT
• Number Of I /o: 28
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x12b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 64-LFCSP
• Controller Family/series: (ARM7) ADUC
• No. Of I/o's: 40
• Ram Memory Size: 8KB
• Cpu Speed: 41.78MHz
• No. Of Timers: 5
• No. Of Pwm Channels: 6
• Package: 64LFCSP EP
• Device Core: ARM7TDMI
• Family Name: ADuC7xxx
• Maximum Speed: 41.78 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 16|32 Bit
• Number Of Programmable I/os: 40
• Interface Type: I2C/SPI/UART
• On-chip Adc: 14-chx12-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-ADUC7128QSPZ - KIT DEV FOR ADUC7128
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

MEMORY ORGANIZATION
The ADuC7128/ADuC7129 incorporate three separate blocks
of memory: 8 kB of SRAM and two 64 kB of on-chip Flash/EE
memory. There are 126 kB of on-chip Flash/EE memory available
to the user, and the remaining 2 kB are reserved for the factory-
configured boot page. These two blocks are mapped as shown
in Figure 29.
Note that by default, after a reset, the Flash/EE memory is
mirrored at Address 0x00000000. It is possible to remap the
SRAM at Address 0x00000000 by clearing Bit 0 of the REMAP
MMR. This remap function is described in more detail in the
Flash/EE Memory section.
MEMORY ACCESS
The ARM7 core sees memory as a linear array of 2 32 byte
locations where the different blocks of memory are mapped as
outlined in Figure 29.
The ADuC7128/ADuC7129 memory organization is configured
in little endian format: the least significant byte is located in the
lowest byte address and the most significant byte in the highest
byte address.
BIT 31
0xFFFF0000
0x00080000
0x00040000
0x00000000
BYTE 3
B
7
3
.
.
.
0xFFFFFFFF
0x0001FFFF
0x00041FFF
0x0009F800
Figure 29. Physical Memory Map
BYTE 2
Figure 30. Little Endian Format
A
6
2
.
.
.
32 BITS
BYTE 1
MMRs
RESERVED
FLASH/EE
RESERVED
SRAM
RESERVED
REMAPPABLE MEMORY SPACE
(FLASH/EE OR SRAM)
9
5
1
.
.
.
BYTE 0
8
4
0
.
.
.
BIT 0
0xFFFFFFFF
0x00000004
0x00000000
Rev. 0 | Page 27 of 92
FLASH/EE MEMORY
The 128 kB of Flash/EE is organized as two banks of 32 k ×
16 bits. In the first block, 31 k × 16 bits are user space and
1 k × 16 bits is reserved for the factory-configured boot
page. The page size of this Flash/EE memory is 512 bytes.
The second 64 kB block is organized in a similar manner. It is
arranged in 32 k × 16 bits. All of this is available as user space.
The 126 kB of Flash/EE is available to the user as code and
nonvolatile data memory. There is no distinction between data
and program as ARM code shares the same space. The real width
of the Flash/EE memory is 16 bits, meaning that in ARM mode
(32-bit instruction), two accesses to the Flash/EE are necessary
for each instruction fetch. Therefore, it is recommended that
Thumb mode be used when executing from Flash/EE memory
for optimum access speed. The maximum access speed for the
Flash/EE memory is 41.78 MHz in Thumb mode and 20.89 MHz
in full ARM mode (see the Execution Time from SRAM and
FLASH/EE section).
SRAM
The 8 kB of SRAM are available to the user, organized as 2 k ×
32 bits, that is, 2 k words. ARM code can run directly from SRAM
at 41.78 MHz, given that the SRAM array is configured as a
32-bit wide memory array (see the Execution Time from SRAM
and FLASH/EE section).
MEMORY MAPPED REGISTERS
The memory mapped register (MMR) space is mapped into the
upper two pages of the memory array and accessed by indirect
addressing through the ARM7 banked registers.
The MMR space provides an interface between the CPU and
all on-chip peripherals. All registers except the core registers
reside in the MMR area. All shaded locations shown in Figure 31
are unoccupied or reserved locations and should not be
accessed by user software. See Table 12 through Table 31 for
a full MMR memory map.
The access time reading or writing a MMR depends on the
advanced microcontroller bus architecture (AMBA) bus used to
access the peripheral. The processor has two AMBA buses:
advanced high performance bus (AHB) used for system modules,
and advanced peripheral bus (APB) used for lower performance
peripherals. Access to the AHB is one cycle, and access to the
APB is two cycles. All peripherals on the ADuC7128/ADuC7129
are on the APB except the Flash/EE memory and the GPIOs.
ADuC7128/ADuC7129