ADUC7128BCPZ126 Analog Devices Inc, ADUC7128BCPZ126 Datasheet - Page 63

• Manufacturer Part Number: ADUC7128BCPZ126
• Description: IC DAS MCU ARM7 ADC/DDS 64-LFCSP
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7128BCPZ126

• Core Size: 16/32-Bit
• Program Memory Size: 126KB (126K x 8)
• Core Processor: ARM7
• Speed: 41.78MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: PLA, POR, PWM, PSM, Temp Sensor, WDT
• Number Of I /o: 28
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x12b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 64-LFCSP
• Controller Family/series: (ARM7) ADUC
• No. Of I/o's: 40
• Ram Memory Size: 8KB
• Cpu Speed: 41.78MHz
• No. Of Timers: 5
• No. Of Pwm Channels: 6
• Package: 64LFCSP EP
• Device Core: ARM7TDMI
• Family Name: ADuC7xxx
• Maximum Speed: 41.78 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 16|32 Bit
• Number Of Programmable I/os: 40
• Interface Type: I2C/SPI/UART
• On-chip Adc: 14-chx12-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-ADUC7128QSPZ - KIT DEV FOR ADUC7128
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

SERIAL PERIPHERAL INTERFACE
The ADuC7128/ADuC7129 integrate a complete hardware
serial peripheral interface (SPI) on-chip. SPI is an industry-
standard synchronous serial interface that allows eight bits
of data to be synchronously transmitted and simultaneously
received, that is, full duplex up to a maximum bit rate of 3.4 Mbs.
The SPI interface is operational only with core clock divider
bits POWCON[2:0] = 0, 1, or 2.
The SPI port can be configured for master or slave operation and
typically consists of four pins, namely: MISO, MOSI, SCL, and CS.
MISO (Master In, Slave Out) Data I/O Pin
The MISO pin is configured as an input line in master mode
and an output line in slave mode. The MISO line on the master
(data in) should be connected to the MISO line in the slave
device (data out). The data is transferred as byte wide (8-bit)
serial data, MSB first.
MOSI (Master Out, Slave In) Pin
The MOSI pin is configured as an output line in master mode
and an input line in slave mode. The MOSI line on the master
(data out) should be connected to the MOSI line in the slave
device (data in). The data is transferred as byte wide (8-bit)
serial data, MSB first.
SCL (Serial Clock) I/O Pin
The master serial clock (SCL) is used to synchronize the data
being transmitted and received through the MOSI SCL period.
Therefore, a byte is transmitted/received after eight SCL periods.
The SCL pin is configured as an output in master mode and as
an input in slave mode.
In master mode, polarity and phase of the clock are controlled
by the SPICON register, and the bit rate is defined in the
SPIDIV register as follows:
In slave mode, the SPICON register must be configured with
the phase and polarity of the expected input clock. The slave
accepts data from an external master up to 3.4 Mbs at CD = 0.
In both master and slave modes, data is transmitted on one edge
of the SCL signal and sampled on the other. Therefore, it is
important that the polarity and phase be configured the same
for the master and slave devices.
The maximum speed of the SPI clock is dependent on the clock
divider bits and is summarized in Table 89.
Table 89. SPI Speed vs. Clock Divider Bits in Master Mode
CD Bits
SPIDIV in hex
SPI speed
in MHz
f
SERIAL
CLOCK
0
0x05
3.482
=
2
×
1 (
1
0x0B
1.741
+
f
HCLK
SPIDIV
2
0x17
0.870
)
3
0x2F
0.435
4
0x5F
0.218
5
0xBF
0.109
Rev. 0 | Page 63 of 92
In slave mode, the SPICON register must be configured with
the phase and polarity of the expected input clock. The slave
accepts data from an external master up to 10.4 Mbs at CD = 0.
The formula to determine the maximum speed follows:
In both master and slave modes, data is transmitted on one edge
of the SCL signal and sampled on the other. Therefore, it is
important that the polarity and phase be configured the same
for the master and slave devices.
Chip Select ( CS ) Input Pin
In SPI slave mode, a transfer is initiated by the assertion of CS ,
which is an active low input signal. The SPI port then transmits
and receives 8-bit data until the transfer is concluded by
desassertion of CS . In slave mode, CS is always an input.
SPI Registers
The following MMR registers are used to control the SPI
interface: SPISTA, SPIRX, SPITX, SPIDIV, and SPICON.
SPISTA Register
Name
SPISTA
SPISTA is an 8-bit read-only status register.
Table 90. SPISTA MMR Bit Designations
Bit
7:6
5
4
3
2
1
0
Description
Reserved.
SPIRX Data Register Overflow Status Bit.
SPIRX Data Register IRQ.
SPIRX Data Register Full Status Bit.
SPITX Data Register Underflow Status Bit.
SPITX Data Register IRQ.
SPITX Data Register Empty Status Bit.
Set if SPIRX is overflowing.
Cleared by reading SPIRX register.
Set automatically if Bit 3 or Bit 5 is set.
Cleared by reading SPIRX register.
Set automatically if valid data is present in the SPIRX
register.
Cleared by reading SPIRX register.
Set automatically if SPITX is underflowing.
Cleared by writing in the SPITX register.
Set automatically if Bit 0 is clear or Bit 2 is set.
Cleared by writing in the SPITX register or if finished
transmission disabling the SPI.
Set by writing to SPITX to send data. This bit is set
during transmission of data.
Cleared when SPITX is empty.
f
SERIAL
Address
0xFFFF0A00
CLOCK
=
f
HCLK
4
ADuC7128/ADuC7129
Default Value
0x00
Access
R