ADUC7128BCPZ126 Analog Devices Inc, ADUC7128BCPZ126 Datasheet - Page 72

• Manufacturer Part Number: ADUC7128BCPZ126
• Description: IC DAS MCU ARM7 ADC/DDS 64-LFCSP
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7128BCPZ126

• Core Size: 16/32-Bit
• Program Memory Size: 126KB (126K x 8)
• Core Processor: ARM7
• Speed: 41.78MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: PLA, POR, PWM, PSM, Temp Sensor, WDT
• Number Of I /o: 28
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x12b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 64-LFCSP
• Controller Family/series: (ARM7) ADUC
• No. Of I/o's: 40
• Ram Memory Size: 8KB
• Cpu Speed: 41.78MHz
• No. Of Timers: 5
• No. Of Pwm Channels: 6
• Package: 64LFCSP EP
• Device Core: ARM7TDMI
• Family Name: ADuC7xxx
• Maximum Speed: 41.78 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 16|32 Bit
• Number Of Programmable I/os: 40
• Interface Type: I2C/SPI/UART
• On-chip Adc: 14-chx12-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-ADUC7128QSPZ - KIT DEV FOR ADUC7128
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

ADuC7128/ADuC7129
PROCESSOR REFERENCE PERIPHERALS
INTERRUPT SYSTEM
There are 30 interrupt sources on the ADuC7128/ADuC7129
controlled by the interrupt controller. Most interrupts are generated
from the on-chip peripherals, such as ADC and UART. Two
additional interrupt sources are generated from external interrupt
request pins, XIRQ0 and XIRQ1. The ARM7TDMI CPU core
only recognizes interrupts as one of two types: a normal interrupt
request (IRQ) or a fast interrupt request (FIQ). All the interrupts
can be masked separately.
The control and configuration of the interrupt system are managed
through nine interrupt-related registers, four dedicated to IRQ,
four dedicated to FIQ, and an additional MMR that is used to
select the programmed interrupt source. The bits in each IRQ
and FIQ register represent the same interrupt source as described
in Table 104.
Table 104. IRQ/FIQ MMRs Bit Designations
Bit
0
1
2
3
4
5
6
7
8
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
9
Description
FIQ Source.
SWI. Not used in IRQEN/CLR and FIQEN/CLR.
Timer0.
Timer1.
Wake-Up Timer—Timer2.
Watchdog Timer—Timer3.
Timer4.
Flash Controller 0.
Flash Controller 1.
ADC.
Quadrature Encoder.
I2C0 Slave.
I2C1 Slave.
I2C0 Master.
I2C1 Master.
SPI Slave.
SPI Master.
UART0.
UART1.
External IRQ0.
Comparator.
PSM.
External IRQ1.
PLA IRQ0.
PLA IRQ1.
External IRQ2.
External IRQ3.
PWM Trip.
PLL Lock.
Reserved.
Reserved.
Rev. 0 | Page 72 of 92
IRQ
The interrupt request (IRQ) is the exception signal to enter the
IRQ mode of the processor. It is used to service general-
purpose interrupt handling of internal and external events.
The four 32-bit registers dedicated to IRQ are listed in Table 105.
Table 105. IRQ Interface MMRs
Register
IRQSIG
IRQEN
IRQCLR
IRQSTA
FIQ
The fast interrupt request (FIQ) is the exception signal to enter
the FIQ mode of the processor. It is provided to service data
transfer or communication channel tasks with low latency. The
FIQ interface is identical to the IRQ interface providing the
second level interrupt (highest priority). Four 32-bit registers
are dedicated to FIQ: FIQSIG, FIQEN, FIQCLR, and FIQSTA.
Bit 31 to Bit 1 of FIQSTA are logically OR’ e d to create the FIQ
signal to the core and Bit 0 of both the FIQ and IRQ registers
(FIQ source).
The logic for FIQEN and FIQCLR does not allow an interrupt
source to be enabled in both IRQ and FIQ masks. A bit set
to 1 in FIQEN, as a side effect, clears the same bit in IRQEN.
A bit set to 1 in IRQEN, as a side effect, clears the same bit
in FIQEN. An interrupt source can be disabled in both IRQEN and
FIQEN masks.
Description
Reflects the status of the different IRQ sources.
If a peripheral generates an IRQ signal, the
corresponding bit in the IRQSIG is set; otherwise,
it is cleared. The IRQSIG bits are cleared when the
interrupt in the particular peripheral is cleared. All
IRQ sources can be masked in the IRQEN MMR.
IRQSIG is read only.
Provides the value of the current enable mask. When
set to 1, the source request is enabled to create an
IRQ exception. When set to 0, the source request is
disabled or masked but does not create an IRQ
exception. To clear a bit in IRQEN, use the IRQCLR MMR.
Write-only register allows clearing the IRQEN register
to mask an interrupt source. Each bit set to 1 clears
the corresponding bit in the IRQEN register without
affecting the remaining bits. The pair of registers,
IRQEN and IRQCLR, allows independent manipulation
of the enable mask without requiring an automatic
read-modify-write.
Read-only register provides the current enabled IRQ
source status. When set to 1, that source should
generate an active IRQ request to the ARM7TDMI
core. There is no priority encoder or interrupt vector
generation. This function is implemented in software
in a common interrupt handler routine. All 32 bits are
logically OR’ed to create the IRQ signal to the
ARM7TDMI core.