ADUC7128BCPZ126 Analog Devices Inc, ADUC7128BCPZ126 Datasheet - Page 44

• Manufacturer Part Number: ADUC7128BCPZ126
• Description: IC DAS MCU ARM7 ADC/DDS 64-LFCSP
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7128BCPZ126

• Core Size: 16/32-Bit
• Program Memory Size: 126KB (126K x 8)
• Core Processor: ARM7
• Speed: 41.78MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: PLA, POR, PWM, PSM, Temp Sensor, WDT
• Number Of I /o: 28
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x12b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 64-LFCSP
• Controller Family/series: (ARM7) ADUC
• No. Of I/o's: 40
• Ram Memory Size: 8KB
• Cpu Speed: 41.78MHz
• No. Of Timers: 5
• No. Of Pwm Channels: 6
• Package: 64LFCSP EP
• Device Core: ARM7TDMI
• Family Name: ADuC7xxx
• Maximum Speed: 41.78 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 16|32 Bit
• Number Of Programmable I/os: 40
• Interface Type: I2C/SPI/UART
• On-chip Adc: 14-chx12-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-ADUC7128QSPZ - KIT DEV FOR ADUC7128
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

ADuC7128/ADuC7129
RESET AND REMAP
The ARM exception vectors are all situated at the bottom of the
memory array, from Address 0x00000000 to Address 0x00000020,
as shown in Figure 45.
By default and after any reset, the Flash/EE is mirrored at the
bottom of the memory array. The remap function allows the
programmer to mirror the SRAM at the bottom of the memory
array, facilitating execution of exception routines from SRAM
instead of from Flash/EE. This means exceptions are executed
twice as fast, with the exception being executed in ARM mode
(32 bits), and the SRAM being 32 bits wide instead of 16-bit
wide Flash/EE memory.
Table 47. REMAP MMR Bit Designations
Bit
0
Table 48. RSTSTA MMR Bit Designations
Bit
7:3
2
1
0
KERNEL
INTERRUPT
SERVICE ROUTINES
INTERRUPT
SERVICE ROUTINES
ARM EXCEPTION
VECTOR ADDRESSES
Name
Remap
Description
Reserved.
Software Reset.
Watchdog Timeout.
Power-On Reset.
Set by user to force a software reset.
Cleared by setting the corresponding bit in RSTCLR.
Set automatically when a watchdog timeout occurs.
Cleared by setting the corresponding bit in RSTCLR.
Set automatically when a power-on reset occurs.
Cleared by setting the corresponding bit in RSTCLR.
Figure 45. Remap for Exception Execution
0x00000020
0x00000000 0x00000000
0x00080000
0x00040000
Description
Remap Bit.
Set by user to remap the SRAM to Address 0x00000000.
Cleared automatically after reset to remap the Flash/EE memory to Address 0x00000000.
0xFFFFFFFF
0x0008FFFF
0x00041FFF
FLASH/EE
SRAM
MIRROR SPACE
Rev. 0 | Page 44 of 92
Remap Operation
When a reset occurs on the ADuC7128/ADuC7129, execution
starts automatically in factory-programmed internal configura-
tion code. This kernel is hidden and cannot be accessed by user
code. If the ADuC7128/ADuC7129 are in normal mode (the BM
pin is high), they execute the power-on configuration routine of
the kernel and then jump to the reset vector Address 0x00000000 to
execute the user’s reset exception routine. Because the Flash/EE is
mirrored at the bottom of the memory array at reset, the reset
interrupt routine must always be written in Flash/EE.
The remap is done from Flash/EE by setting Bit 0 of the REMAP
register. Precautions must be taken to execute this command
from Flash/EE, above Address 0x00080020, and not from the
bottom of the array because this is replaced by the SRAM.
This operation is reversible: the Flash/EE can be remapped at
Address 0x00000000 by clearing Bit 0 of the REMAP MMR.
Precaution must again be taken to execute the remap function
from outside the mirrored area. Any kind of reset remaps the
Flash/EE memory at the bottom of the array.
Reset Operation
There are four kinds of reset: external reset, power-on reset,
watchdog expiration, and software force. The RSTSTA register
indicates the source of the last reset and RSTCLR clears the
RSTSTA register. These registers can be used during a reset
exception service routine to identify the source of the reset.
If RSTSTA is null, the reset was external. Note that when
clearing RSTSTA, all bits that are currently 1 must be cleared.
Otherwise, a reset event occurs.