ADUC7128BCPZ126 Analog Devices Inc, ADUC7128BCPZ126 Datasheet - Page 59

• Manufacturer Part Number: ADUC7128BCPZ126
• Description: IC DAS MCU ARM7 ADC/DDS 64-LFCSP
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7128BCPZ126

• Core Size: 16/32-Bit
• Program Memory Size: 126KB (126K x 8)
• Core Processor: ARM7
• Speed: 41.78MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: PLA, POR, PWM, PSM, Temp Sensor, WDT
• Number Of I /o: 28
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x12b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 64-LFCSP
• Controller Family/series: (ARM7) ADUC
• No. Of I/o's: 40
• Ram Memory Size: 8KB
• Cpu Speed: 41.78MHz
• No. Of Timers: 5
• No. Of Pwm Channels: 6
• Package: 64LFCSP EP
• Device Core: ARM7TDMI
• Family Name: ADuC7xxx
• Maximum Speed: 41.78 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 16|32 Bit
• Number Of Programmable I/os: 40
• Interface Type: I2C/SPI/UART
• On-chip Adc: 14-chx12-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-ADUC7128QSPZ - KIT DEV FOR ADUC7128
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Table 80. COMxCON0 MMR Bit Designations
Bit
7
6
5
4
3
2
1:0
Table 81. COMxSTA0 MMR Bit Designations
Bit
7
6
5
4
3
2
1
0
Value
00
01
10
11
Name
RSVD
TEMT
THRE
BI
FE
PE
OE
DR
Name
DLAB
BRK
SP
EPS
PEN
STOP
WLS
Description
Divisor Latch Access.
Set Break.
Stick Parity.
Even Parity Select Bit.
Parity Enable Bit.
Stop Bit.
Word Length Select.
5 bits.
6 bits.
7 bits.
8 bits.
Description
Reserved.
COMxTX Empty Status Bit.
COMxTX and COMxRX Empty.
Break Error.
Framing Error.
Parity Error.
Overrun Error.
Data Ready.
Set by user to enable access to COMxDIV0 and COMxDIV1 registers.
Cleared by user to disable access to COMxDIV0 and COMxDIV1 and enable access to COMxRX and COMxTX.
Set by user to force SOUT to 0.
Cleared to operate in normal mode.
Set by user to force parity to defined values.
Set for even parity.
Cleared for odd parity.
Set by user to transmit and check the parity bit.
Cleared by user for no parity transmission or checking.
Set by user to transmit 1.5 stop bits if the word length is 5 bits or 2 stop bits if the word length is 6 bits, 7 bits, or
8 bits. The receiver checks the first stop bit only, regardless of the number of stop bits selected.
Cleared by user to generate 1 stop bit in the transmitted data.
Set automatically if COMxTX is empty.
Cleared automatically when writing to COMxTX.
Set automatically if COMxTX and COMxRX are empty.
Cleared automatically when one of the registers receives data.
Set when SIN is held low for more than the maximum word length.
Cleared automatically.
Set when stop bit invalid.
Cleared automatically.
Set when a parity error occurs.
Cleared automatically.
Set automatically if data is overwritten before it is read.
Cleared automatically.
Set automatically when COMxRX is full.
Cleared by reading COMxRX.
1 if EPS = 1 and PEN = 1
0 if EPS = 0 and PEN = 1
Rev. 0 | Page 59 of 92
ADuC7128/ADuC7129