EP9307-IRZ Cirrus Logic Inc, EP9307-IRZ Datasheet - Page 125

• Manufacturer Part Number: EP9307-IRZ
• Description: IC ARM9 SOC ARM920T 272TFBGA
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9307-IRZ

• Core Size: 16/32-Bit
• Core Processor: ARM9
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 14
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 272-TFBGA
• Controller Family/series: (ARM9)
• No. Of I/o's: 14
• Ram Memory Size: 32MB
• Cpu Speed: 200MHz
• No. Of Timers: 3
• No. Of Pwm Channels: 1
• Digital Ic Case Style: TFBGA
• Embedded Interface Type: AC97, I2S, SPI, UART, USB
• Rohs Compliant: Yes
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9307A-Z
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1133 - KIT DEVELOPMENT EP9307 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1256

DS785UM1
4.2.4 SDRAM or SyncFLASH Boot
4.2.5 Synchronous Memory Operation
0x3000_1000
0x6000_0000
0x7000_0000
Code execution will start at address FLASH base + 0x0. The ARM Core will be in SVC mode.
To enable SDRAM or SyncFLASH boot, make sure that the pins are configured for normal
boot mode, as shown in
make sure the SDRAM or SyncFLASH word size is correct, as shown in
with a 16-bit SDRAM device, follow the suggested software sequence of commands, as
shown in
To boot from SDRAM or SyncFLASH, put the ASCII “CRUS” or “SURC” value in the
HeaderID at one of the following locations (this location is Base + 0x0):
0xC000_0000
0xF000_0000
Code execution will start at address Base + 0x4. The ARM Core will be in SVC mode.
Alternatively, to boot from SDRAM or SyncFLASH, put the ASCII “CRUS” or “SURC” value in
the HeaderID at one of the following locations (this is Base + 0x1000):
0xC000_1000
0xF000_1000
Code execution will start at address Base + 0x0. The ARM Core will be in SVC mode.
If running from Synchronous memory, before issuing a software reset, perform this
procedure:
Note: CSn6 is the recommended chip select for Flash when performing an Internal boot. CSn0
1. Run from SDRAM
2. Perform a software reset (SWRST bit in DEVCFG register)
must be connected to Flash when performing an External boot.
Figure
Figure 4-2. Flow chart of Boot Sequence for 16-bit SDRAM Devices
4-2.
Boot Internally with Asynchronous Device
Figure
Re-configure SDRAM for 16-bit access
Branch to desired SDRAM memory
Copyright 2007 Cirrus Logic
4-2. If booting with SyncFLASH or a 32-bit SDRAM device,
Figure
EP93xx User’s Guide
4-2. If booting
Boot ROM
4-7
4