EP9307-IRZ Cirrus Logic Inc, EP9307-IRZ Datasheet - Page 213

• Manufacturer Part Number: EP9307-IRZ
• Description: IC ARM9 SOC ARM920T 272TFBGA
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9307-IRZ

• Core Size: 16/32-Bit
• Core Processor: ARM9
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 14
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 272-TFBGA
• Controller Family/series: (ARM9)
• No. Of I/o's: 14
• Ram Memory Size: 32MB
• Cpu Speed: 200MHz
• No. Of Timers: 3
• No. Of Pwm Channels: 1
• Digital Ic Case Style: TFBGA
• Embedded Interface Type: AC97, I2S, SPI, UART, USB
• Rohs Compliant: Yes
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9307A-Z
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1133 - KIT DEVELOPMENT EP9307 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1256

DS785UM1
7.4.10.1.1 Setting up the VidScrnPage Register
7.4.10.1.2 Setting up the ScrnLines Register
7.4.10.1.3 Setting up the LineLength Register
7.4.10.1.4 Setting up the VLineStep Register
7.4.10.1.5 Memory Setup Example
7.4.10.1 Setting the Video Memory Parameters
The Raster Engine uses SDRAM for video frame buffers. The SDRAM locations for the video
frame buffers are defined by four registers:
“VLineStep”
The
beginning of SDRAM memory space. With the combination of SDSEL in
it forms the absolute address for the starting location of the video memory. It is possible to
provide for a panning feature by altering the address of the start location at run time. This
address also represents the 0,0 pixel position, which is in the upper left corner of the video
image.
The
LineLength size that are to be fetched and forwarded to the FIFO. The ‘number of lines’ must
be programmed to be one less than the desired number of lines, because a programmed
value of 0x0 specifies a single line. The maximum value is 0x7FF for 2048 lines.
The
fetch from SDRAM for each scan line. This value is always one less than the needed number
of 32-bit words because a programmed value of 0x0 specifies a single 32-bit word.
For example, a display width of eighty 8-bit pixels requires that twenty 32-bit words be
fetched from the SDRAM video frame buffer for each scan line, since four 8-bit pixels can be
packed into a single 32-bit word (80/4=20).
At the end of fetching LineLength of data for the first scan line, the Raster Engine will take the
value in the
determine the starting SDRAM address for the next scan line. Generally, this value is the
same as LineLength + 0x1. However, it is possible to have an image in SDRAM that is larger
then the current display. This larger image can be cropped by the proper programming of
“VidScrnPage”
Assume that a video display is 640 x 480 with a color depth of 4 bpp and that the start of
video memory (display pixel coordinate 0,0) is the address determined by SDSEL + 0x1000.
The register settings for this example are:
VidScrnPage
“ScrnLines”
“LineLength”
“VLineStep”
.
,
“VLineStep”
register is used by the Raster Engine to specify the number of lines of
VidScrnPage = 0x1000 (assume SDSEL = 0)
ScrnLines = 480 - 1 = 479 = 0x1DF
LineLength = (640 x 4bpp / 32) - 1 = 79 = 0x4F
register provides the starting address for the video memory relative to the
register contains the number of 32-bit words that the Raster Engine must
register and add it to the base address
, and
Copyright 2007 Cirrus Logic
“ScrnLines”
Raster Engine With Analog/LCD Integrated Timing and Interface
“VidScrnPage”
registers.
,
“ScrnLines”
(“VidScrnPage”
VideoAttribs
,
“LineLength”
EP93xx User’s Guide
) to
register,
, and
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