EP9307-IRZ Cirrus Logic Inc, EP9307-IRZ Datasheet - Page 9
EP9307-IRZ
Manufacturer Part Number
EP9307-IRZ
Description
IC ARM9 SOC ARM920T 272TFBGA
Manufacturer
Cirrus Logic Inc
Series
EP9r
Datasheets
1.EP9307-CRZ.pdf
(16 pages)
2.EP9307-CRZ.pdf
(50 pages)
3.EP9307-CRZ.pdf
(824 pages)
4.EP9307-CRZ.pdf
(48 pages)
Specifications of EP9307-IRZ
Core Size
16/32-Bit
Core Processor
ARM9
Speed
200MHz
Connectivity
EBI/EMI, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LCD, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
14
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
272-TFBGA
Controller Family/series
(ARM9)
No. Of I/o's
14
Ram Memory Size
32MB
Cpu Speed
200MHz
No. Of Timers
3
No. Of Pwm Channels
1
Digital Ic Case Style
TFBGA
Embedded Interface Type
AC97, I2S, SPI, UART, USB
Rohs Compliant
Yes
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
EDB9307A-Z
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
598-1133 - KIT DEVELOPMENT EP9307 ARM9
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Other names
598-1256
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP9307-IRZ
Manufacturer:
CIRRUS
Quantity:
3 468
Company:
Part Number:
EP9307-IRZR
Manufacturer:
Cirrus Logic Inc
Quantity:
10 000
- EP9307-CRZ PDF datasheet
- EP9307-CRZ PDF datasheet #2
- EP9307-CRZ PDF datasheet #3
- EP9307-CRZ PDF datasheet #4
- Current page: 9 of 824
- Download datasheet (13Mb)
Chapter 12. Static Memory Controller ............................................................... 12-1
Chapter 13. SDRAM, SyncROM, and SyncFLASH Controller.......................... 13-1
Chapter 14. UART1 With HDLC and Modem Control Signals.......................... 14-1
DS785UM1
11.3 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-11
12.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-1
12.2 Static Memory Controller Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-2
12.3 PCMCIA Interface (EP9315 Processor Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-5
12.4 PC Card Memory-Mode Enable Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-8
12.5 PC Card Memory Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-8
12.6 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-10
13.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-1
13.2 Booting from SyncROM or SyncFLASH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-1
13.3 Address Pin Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-3
13.4 SDRAM Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-4
13.5 Programming Mode Register: SDRAM Or SyncROM Device. . . . . . . . . . . . . . . . . . . . . . .13-6
13.6 SDRAM Self Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-8
13.7 Programming Registers: SyncFLASH Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-8
13.8 External Synchronous Memory System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-9
13.9 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-17
14.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-1
14.2 UART Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-1
11.2.4 Host Controller Responsibilities...................................................................................11-8
11.2.5 USB Host Controller Blocks.........................................................................................11-9
12.6.1 Bank Configuration Registers....................................................................................12-10
12.6.2 PCMCIA Configuration Registers (EP9315 Processor Only) ....................................12-13
13.6.1 Entering Self Refresh Mode ........................................................................................13-8
13.6.2 Exiting Self Refresh Mode ...........................................................................................13-8
13.8.1 Chip Select SDCSN[3:0] Decoding .............................................................................13-9
13.8.2 Address/Data/Control Required by Memory System.................................................13-10
14.2.1 UART Functional Description ......................................................................................14-2
11.2.4.1 USB States ................................................................................................11-8
11.2.4.2 Frame Management ..................................................................................11-8
11.2.4.3 List Processing ..........................................................................................11-8
11.2.5.1 AHB Slave .................................................................................................11-9
11.2.5.2 AHB Master ...............................................................................................11-9
11.2.5.3 HCI Slave Block.........................................................................................11-9
11.2.5.4 HCI Master Block.....................................................................................11-10
11.2.5.5 USB State Control ...................................................................................11-10
11.2.5.6 Data FIFO ................................................................................................11-10
11.2.5.7 List Processor ..........................................................................................11-10
11.2.5.8 Root Hub and Host SIE ...........................................................................11-10
14.2.1.1 AMBA APB Interface .................................................................................14-2
14.2.1.2 DMA Block .................................................................................................14-2
14.2.1.3 Register Block............................................................................................14-2
14.2.1.4 Baud Rate Generator.................................................................................14-4
14.2.1.5 Transmit FIFO............................................................................................14-4
14.2.1.6 Receive FIFO.............................................................................................14-4
14.2.1.7 Transmit Logic ...........................................................................................14-4
14.2.1.8 Receive Logic ............................................................................................14-4
©
Copyright 2007 Cirrus Logic, Inc.
EP93xx User’s Guide
ix
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