ST7FLITE20F1B6 STMicroelectronics, ST7FLITE20F1B6 Datasheet - Page 52

IC MCU 8BIT 8K FLASH 20-DIP

ST7FLITE20F1B6

Manufacturer Part Number
ST7FLITE20F1B6
Description
IC MCU 8BIT 8K FLASH 20-DIP
Manufacturer
STMicroelectronics
Series
ST7r
Datasheets

Specifications of ST7FLITE20F1B6

Core Processor
ST7
Core Size
8-Bit
Speed
8MHz
Connectivity
SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
15
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
384 x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 5.5 V
Data Converters
A/D 7x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-DIP (0.300", 7.62mm)
Processor Series
ST7FLITE2x
Core
ST7
Data Bus Width
8 bit
Development Tools By Supplier
ST7FLITE-SK/RAIS, ST7MDT10-DVP3, ST7MDT10-EMU3, STX-RLINK
For Use With
497-5858 - EVAL BOARD PLAYBACK ST7FLITE497-5517 - EVAL BOARD 1PHASE ENERGY METER497-5049 - KIT STARTER RAISONANCE ST7FLITE
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details

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Function Descriptions
Table 28. SCI2_ClkConfigure
52/235
Function Name
Function Prototype
Behaviour Description
Input Parameter 1
Input Parameter 2
Output Parameters
Required Preconditions.
Functions called
Postconditions
See also
Void SCI2_ClkConfigure(SCI_PO_PH_t
SCI_PO_PH_Param, SCI_LBCL_t SCI_LBCL_Param)
Configures the Polarity, Phase and numbers of Clock
pulses for the SCI2 Clock out.
SCI_PO_LOW_PH_LOW
Default value on CLK pin low
CLK activated at the in the middle of data bit
SCI_PO_LOW_PH_HIGH
Default value on CLK pin low
CLK activated at the beginning of data bit
SCI_PO_HIGH_PH_LOW
Default value on CLK pin High
CLK activated in the middle of data bit
SCI_PO_HIGH_PH_HIGH
Default value on CLK pin high
CLK activated at the beginning of data bit
SCI_LBCL_DISABLE
The CLK pulse of last data bit is not output to the pin
SCI_LBCL_ENABLE
The CLK pulse of last data bit is output to the pin
None
None
None
SCI clock is availaible at a dedicated pin during communi-
cation.
None
SCI2_ClkConfigure

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