ST7FDALIF2M6 STMicroelectronics, ST7FDALIF2M6 Datasheet - Page 169

• Manufacturer Part Number: ST7FDALIF2M6
• Description: IC MCU 8BIT 8K 20-SOIC
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST7FDALIF2M6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: DALI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 15
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 5.5 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-SOIC (7.5mm Width)
• Processor Series: ST7DALI
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 384 B
• Interface Type: DALI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 15
• Number Of Timers: 4 bit
• Operating Supply Voltage: 2.4 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST7FLITE-SK/RAIS, ST7DALI-EVAL, ST7MDT10-DVP3, ST7MDT10-EMU3, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit
• For Use With: 497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-2131-5

ST7DALIF2
Table 100. Document revision history (continued)
19-Nov-2004
Date
Revision
2
Reset delay in section 11.1.3 on page 51 changed to 30 µs
Altered note 1 for section 13.2.3 on page 101 removing references to
RESET
Removed sentence relating to an effective change only after overflow
for CK[1:0],
MOD00 replaced by 0Ex in
Added Note 2 related to Exit from Active halt,
59
Added illegal opcode detection to page 1,
section 12 on page 94
Clarification of Flash readout protection,
Added note 4 and description relating to Total Percentage in Error
and Amplifier Output Offset
Variation to the ADC Characteristics subsection and table,
Added note 5 and description relating to Offset Variation in
Temperature to ADC Characteristics subsection and table,
FPLL value of 1MHz quoted as Typical instead of a Minimum in
section 13.3.4.1 on page 104
Updated FSCK in
Corrected f
page 108
Max values updated for ADC Accuracy,
Notes indicating that PB4 cannot be used as an external interrupt in
HALT mode,
on page 138
Changed
Changed
Removed “optional” referring to VDD in
Changed FMP_R option bit description in
Added “Clearing active interrupts outside interrupt routine” on page
138
Changed “Development Tools” on page 134
Changed
section 11.5.2 on page 79
section 11.5.3.3 on page 82
Figure 41 on page
CPU
page 60
section 16.6
and
in Slow and slow wait modes in
Section 8.3 PERIPHERAL INTERRUPTS
section 13.10.1 on page 121
Figure 36 on page 57
70: f
Changes
CPU
instead of 8 MHz f
Figure 4 on page 13
page 124
section 4.5.1 on page 14
section 15.1 on page 130
section 7.6 on page
section 11.2.5 on page
to f
section 13.4.1 on
Revision history
CPU
/4 and f
CPU
page 126
page 126
169/171
CPU
29,
/2