ST7FDALIF2M6 STMicroelectronics, ST7FDALIF2M6 Datasheet - Page 55

• Manufacturer Part Number: ST7FDALIF2M6
• Description: IC MCU 8BIT 8K 20-SOIC
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST7FDALIF2M6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: DALI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 15
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 5.5 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-SOIC (7.5mm Width)
• Processor Series: ST7DALI
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 384 B
• Interface Type: DALI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 15
• Number Of Timers: 4 bit
• Operating Supply Voltage: 2.4 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST7FLITE-SK/RAIS, ST7DALI-EVAL, ST7MDT10-DVP3, ST7MDT10-EMU3, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit
• For Use With: 497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-2131-5

ST7DALIF2
Note:
As soon as Active-halt is enabled, executing a HALT instruction while the Watchdog is active
does not generate a RESET.
This means that the device cannot spend more than a defined delay in this power saving
mode.
Figure 25. Active-halt timing overview
Figure 26. Active-halt mode flowchart
Notes:
1. 1. This delay occurs only if the MCU exits Active-halt mode by means of a RESET.
2. Peripherals clocked with an external clock source can still be active.
3. Only the RTC1 interrupt and some specific interrupts can exit the MCU from Active-halt mode. Refer to
4. Before servicing an interrupt, the CC register is pushed on the stack. The I bit of the CC register is set
Table 15: Interrupt mapping on page 47
during the interrupt routine and cleared when the CC register is popped.
[Active-halt enabled]
(AWUCSR.AWUEN=0)
HALT INSTRUCTION
INSTRUCTION
(Active-halt enabled)
RUN
N
HALT
INTERRUPT
ACTIVE
HALT
Y
for more details.
256 OR 4096 CPU
CYCLE DELAY
INTERRUPT
3)
RESET
256 OR 4096 CPU CLOCK
OR SERVICE INTERRUPT
FETCH RESET VECTOR
OR
OSCILLATOR
PERIPHERALS
CPU
OSCILLATOR
PERIPHERALS
CPU
OSCILLATOR
PERIPHERALS
CPU
I BIT
I BIT
I BIT
N
CYCLE
1)
RESET
Y
VECTOR
FETCH
DELAY
RUN
2)
2)
OFF
OFF
OFF
ON
ON
ON
X
ON
ON
ON
X
0
4)
4)
Power saving modes
55/171