ST7FDALIF2M6 STMicroelectronics, ST7FDALIF2M6 Datasheet - Page 88

• Manufacturer Part Number: ST7FDALIF2M6
• Description: IC MCU 8BIT 8K 20-SOIC
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST7FDALIF2M6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: DALI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 15
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 5.5 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-SOIC (7.5mm Width)
• Processor Series: ST7DALI
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 384 B
• Interface Type: DALI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 15
• Number Of Timers: 4 bit
• Operating Supply Voltage: 2.4 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST7FLITE-SK/RAIS, ST7DALI-EVAL, ST7MDT10-DVP3, ST7MDT10-EMU3, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit
• For Use With: 497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-2131-5

Lite timer 2 (LT2)
15.6.5
88/171
Bit 5 = TB Timebase period selection.
This bit is set and cleared by software.
0: Timebase period = t
1: Timebase period = t
Bit 4 = TB1IE Timebase Interrupt enable.
This bit is set and cleared by software.
0: Timebase (TB1) interrupt disabled
1: Timebase (TB1) interrupt enabled
Bit 3 = TB1F Timebase Interrupt Flag.
This bit is set by hardware and cleared by software reading the LTCSR register. Writing to
this bit has no effect.
0: No counter overflow
1: A counter overflow has occurred
Bits 2:0 = Reserved
Lite timer input capture register (LTICR)
Read only
Reset Value: 0000 0000 (00h)
Bits 7:0 = ICR[7:0] Input Capture Value
These bits are read by software and cleared by hardware after a reset. If the ICF bit in the
LTCSR is cleared, the value of the 8-bit up-counter will be captured when a rising or falling
edge occurs on the LTIC pin.
Table 42.
Address
(Hex.)
ICR7
0A
08
09
7
LTCSR2
Reset
Value
LTARR
Reset
Value
LTCNTR
Reset
Value
Register
Lite timer register map and reset values
label
ICR6
OSC
OSC
CNT7
AR7
7
0
0
0
ICR5
* 8000 (1ms @ 8 MHz)
* 16000 (2ms @ 8 MHz)
CNT6
AR6
6
0
0
0
ICR4
CNT5
AR5
5
0
0
0
ICR3
CNT4
AR4
4
0
0
0
CNT3
AR3
3
0
0
0
ICR2
CNT2
AR2
2
0
0
0
ICR1
TB2IE
CNT1
AR1
1
0
0
0
ST7DALIF2
ICR0
CNT0
TB2F
AR0
0
0
0
0
0