ST72F621L4M1 STMicroelectronics, ST72F621L4M1 Datasheet - Page 21

• Manufacturer Part Number: ST72F621L4M1
• Description: IC MCU 8BIT LS 16K 34-SOIC
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72F621L4M1

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 34-SOIC (7.5mm Width)
• Processor Series: ST72F6x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: SCI, SPI, USB
• Maximum Clock Frequency: 12 MHz
• Number Of Programmable I/os: 23
• Number Of Timers: 2
• Operating Supply Voltage: 4 V to 5.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit
• For Use With: 497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: In Transition
• Other names: 497-2112-5

Figure 14. Clock block diagram
6.2 RESET
The Reset procedure is used to provide an orderly
software start-up or to exit low power modes.
Three reset modes are provided: a low voltage re-
set, a watchdog reset and an external reset at the
RESET pin.
A reset causes the reset vector to be fetched from
addresses FFFEh and FFFFh in order to be loaded
into the PC and with program execution starting
from this point.
An internal circuitry provides a 514 CPU clock cy-
cle delay from the time that the oscillator becomes
active.
Caution: When the ST7 is unprogrammed or fully
erased, the Flash is blank and the RESET vector
is not programmed. For this reason, it is recom-
mended to keep the RESET pin in low state until
programming mode is entered, in order to avoid
unwanted behaviour.
6.2.1 Low Voltage Reset
Low voltage reset circuitry generates a reset when
V
■
■
During low voltage reset, the RESET pin is held low,
thus permitting the MCU to reset other devices.
Notes:
The Low Voltage Detector can be disabled by set-
ting the LVD bit of the Option byte.
DD
below V
below V
is:
IT+
IT-
when V
when V
DD
DD
is falling.
is rising,
Crystal
6 MHz
12 or
%3
x2
%2
SMS[1:0]
1/2/4/8
Mode
Doc ID 6996 Rev 5
Slow
OSC12/6
%
0
1
It is recommended to make sure that the V
voltage rises monotonously when the device is ex-
iting from Reset, to ensure the application functions
properly.
6.2.2 Watchdog Reset
When a watchdog reset occurs, the RESET pin is
pulled low permitting the MCU to reset other devic-
es as when low voltage reset
6.2.3 External Reset
The external reset is an active low input signal ap-
plied to the RESET pin of the MCU.
As shown in
stay low for a minimum of one and a half CPU
clock cycles.
An internal Schmitt trigger at the RESET pin is pro-
vided to improve noise immunity.
Figure 15. Low Voltage Reset functional Diagram
V
DD
(or 4/2/1/0.5 MHz)
f
to CPU and
peripherals
CPU
8/4/2/1 MHz
6 MHz (USB)
LOW VOLTAGE
WATCHDOG
MCO pin
Figure
RESET
RESET
FROM
18, the RESET signal must
(Figure
ST7262xxx
15).
INTERNAL
DD
RESET
RESET
supply
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