ST72F621L4M1 STMicroelectronics, ST72F621L4M1 Datasheet - Page 51

• Manufacturer Part Number: ST72F621L4M1
• Description: IC MCU 8BIT LS 16K 34-SOIC
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72F621L4M1

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 34-SOIC (7.5mm Width)
• Processor Series: ST72F6x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: SCI, SPI, USB
• Maximum Clock Frequency: 12 MHz
• Number Of Programmable I/os: 23
• Number Of Timers: 2
• Operating Supply Voltage: 4 V to 5.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit
• For Use With: 497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: In Transition
• Other names: 497-2112-5

PWM AUTO-RELOAD TIMER (Cont’d)
INPUT CAPTURE
CONTROL / STATUS REGISTER (ARTICCSR)
Read/Write (except bits 1:0 read and clear)
Reset Value: 0000 0000 (00h)
Bit 7:6 = Reserved, always read as 0.
Bit 5:4 = CS[2:1] Capture Sensitivity
These bits are set and cleared by software. They
determine the trigger event polarity on the corre-
sponding input capture channel.
0: Falling edge triggers capture on channel x.
1: Rising edge triggers capture on channel x.
Bit 3:2 = CIE[2:1] Capture Interrupt Enable
These bits are set and cleared by software. They
enable or disable the Input capture channel inter-
rupts independently.
0: Input capture channel x interrupt disabled.
1: Input capture channel x interrupt enabled.
Bit 1:0 = CF[2:1] Capture Flag
These bits are set by hardware when a capture oc-
curs and cleared by hardware when software
reads the ARTICCSR register. Each CFx bit indi-
cates that an input capture x has occurred.
0: No input capture on channel x.
1: An input capture has occurred on channel x.
7
0
0
CS2
CS1
CIE2
CIE1
CF2
CF1
0
Doc ID 6996 Rev 5
INPUT CAPTURE REGISTERS (ARTICRx)
Read only
Reset Value: 0000 0000 (00h)
Bit 7:0 = IC[7:0] Input Capture Data
These read only bits are set and cleared by hard-
ware. An ARTICRx register contains the 8-bit
auto-reload counter value transferred by the input
capture channel x event.
IC7
7
IC6
IC5
IC4
IC3
IC2
ST7262xxx
IC1
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IC0
0