ST72F621L4M1 STMicroelectronics, ST72F621L4M1 Datasheet - Page 94
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ST72F621L4M1
Manufacturer Part Number
ST72F621L4M1
Description
IC MCU 8BIT LS 16K 34-SOIC
Manufacturer
STMicroelectronics
Series
ST7r
Datasheet
1.ST72F622L2M1.pdf
(139 pages)
Specifications of ST72F621L4M1
Core Processor
ST7
Core Size
8-Bit
Speed
8MHz
Connectivity
SCI, SPI, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
34-SOIC (7.5mm Width)
Processor Series
ST72F6x
Core
ST7
Data Bus Width
8 bit
Data Ram Size
768 B
Interface Type
SCI, SPI, USB
Maximum Clock Frequency
12 MHz
Number Of Programmable I/os
23
Number Of Timers
2
Operating Supply Voltage
4 V to 5.5 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
0 C
On-chip Adc
10 bit
For Use With
497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
In Transition
Other names
497-2112-5
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ST72F621L4M1
Manufacturer:
ST
Quantity:
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Part Number:
ST72F621L4M1
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Quantity:
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10-BIT A/D CONVERTER (ADC) (Cont’d)
10.7.6 Register Description
CONTROL/STATUS REGISTER (ADCCSR)
Read/Write (Except bit 7 read only)
Reset Value: 0000 0000 (00h)
Bit 7 = EOC End of Conversion
This bit is set by hardware. It is cleared by soft-
ware reading the ADCDRMSB register.
0: Conversion is not complete
1: Conversion complete
Bit 6 = SPEED ADC clock selection
This bit is set and cleared by software.
0: f
1: f
Bit 5 = ADON A/D Converter on
This bit is set and cleared by software or by hard-
ware after the end of a one shot conversion.
0: Disable ADC and stop conversion
1: Enable ADC and start conversion
Bit 4 = ITE Interrupt Enable
This bit is set and cleared by software.
0: EOC Interrupt disabled
1: EOC Interrupt enabled
Bit 3 = ONESHOT One Shot Conversion Selection
This bit is set and cleared by software.
0: Continuous conversion mode
1: One Shot conversion mode
94/139
EOC SPEED ADON
7
ADC
ADC
= f
= f
CPU
CPU
/2
/4
ITE
SHOT
ONE
CS2
CS1
CS0
0
Doc ID 6996 Rev 5
Bit 2:0 = CS[2:0] Channel Selection
These bits are set and cleared by software. They
select the analog input to convert.
*The number of channels is device dependent. Refer to
the device pinout description.
DATA REGISTER (ADCDRMSB)
Read Only
Reset Value: 0000 0000 (00h)
Bit 7:0 = D[9:2] MSB of Analog Converted Value
This register contains the MSB of the converted
analog value.
DATA REGISTER (ADCDRLSB)
Read Only
Reset Value: 0000 0000 (00h)
Bit 7:2 = Reserved. Forced by hardware to 0.
Bit 1:0 = D[1:0] LSB of Analog Converted Value
This register contains the LSB of the converted an-
alog value.
Note: please refer to
NOTES
D9
7
7
0
D8
0
Channel*
0
1
2
3
4
5
6
7
D7
0
D6
0
Section 15 IMPORTANT
D5
0
CS2
0
0
0
0
1
1
1
1
D4
0
CS1
0
0
1
1
0
0
1
1
D3
D1
CS0
0
1
0
1
0
1
0
1
D2
D0
0
0