MC9S08SL16CTL Freescale Semiconductor, MC9S08SL16CTL Datasheet - Page 105

• Manufacturer Part Number: MC9S08SL16CTL
• Description: MCU 16KB FLASH SLIC 28TSSOP
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08SL16CTL

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-TSSOP
• Processor Series: S08SL
• Core: HCS08
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: I2C/SCI/SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 22
• Number Of Timers: 6
• Operating Supply Voltage: 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWS08
• Development Tools By Supplier: DEMO9S08EL32, DEMO9S08EL32AUTO
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• Package: 28TSSOP
• Family Name: HCS08
• Maximum Speed: 40 MHz
• For Use With: DEMO9S08EL32 - BOARD DEMO FOR 9S08 EL MCUDEMO9S08EL32AUTO - DEMO BOARD EL32 AUTO
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Freescale Semiconductor
BLE rel
BLO rel
BLS rel
BLT rel
BMC rel
BMI rel
BMS rel
BNE rel
BPL rel
BRA rel
BRCLR n,opr8a,rel
BRN rel
BRSET n,opr8a,rel
BSET n,opr8a
BSR rel
CBEQ opr8a,rel
CBEQA #opr8i,rel
CBEQX #opr8i,rel
CBEQ oprx8,X+,rel
CBEQ ,X+,rel
CBEQ oprx8,SP,rel
Source
Form
Branch if Less Than or Equal To
(if Z | (N ⊕ V) = 1) (Signed)
Branch if Lower (if C = 1) (Same as BCS)
Branch if Lower or Same (if C | Z = 1)
Branch if Less Than (if N ⊕ V = 1) (Signed)
Branch if Interrupt Mask Clear (if I = 0)
Branch if Minus (if N = 1)
Branch if Interrupt Mask Set (if I = 1)
Branch if Not Equal (if Z = 0)
Branch if Plus (if N = 0)
Branch Always (if I = 1)
Branch if Bit n in Memory Clear (if (Mn) = 0)
Branch Never (if I = 0)
Branch if Bit n in Memory Set (if (Mn) = 1)
Set Bit n in Memory (Mn ← 1)
Branch to Subroutine
Compare and...
push (PCH); SP ← (SP) – $0001
push (PCL); SP ← (SP) – $0001
MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3
PC ← (PC) + $0002
PC ← (PC) + rel
Table 7-2. Instruction Set Summary (Sheet 3 of 9)
Operation
Branch if (A) = (M)
Branch if (A) = (M)
Branch if (X) = (M)
Branch if (A) = (M)
Branch if (A) = (M)
Branch if (A) = (M)
REL
REL
REL
REL
REL
REL
REL
REL
REL
REL
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
REL
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
REL
DIR
IMM
IMM
IX1+
IX+
SP1
Object Code
9E 61
93 rr
25 rr
23 rr
91 rr
2C rr
2B rr
2D rr
26 rr
2A rr
20 rr
01
03
05
07
09
0B
0D
0F
21 rr
00
02
04
06
08
0A
0C
0E
10
12
14
16
18
1A
1C
1E
AD rr
31
41
51
61
71
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd
dd
dd
dd
dd
dd
dd
dd
dd rr
ii rr
ii rr
ff rr
rr
ff rr
Chapter 7 Central Processor Unit (S08CPUV3)
3
3
3
3
3
3
3
3
3
3
5
5
5
5
5
5
5
5
3
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
4
4
5
5
6
ppp
ppp
ppp
ppp
ppp
ppp
ppp
ppp
ppp
ppp
rpppp
rpppp
rpppp
rpppp
rpppp
rpppp
rpppp
rpppp
ppp
rpppp
rpppp
rpppp
rpppp
rpppp
rpppp
rpppp
rpppp
rfwpp
rfwpp
rfwpp
rfwpp
rfwpp
rfwpp
rfwpp
rfwpp
ssppp
rpppp
pppp
pppp
rpppp
rfppp
prpppp
Cyc-by-Cyc
Details
V 1 1 H I N Z C
– 1 1 – – – – –
– 1 1 – – – – –
– 1 1 – – – – –
– 1 1 – – – – –
– 1 1 – – – – –
– 1 1 – – – – –
– 1 1 – – – – –
– 1 1 – – – – –
– 1 1 – – – – –
– 1 1 – – – – –
– 1 1 – – – –
– 1 1 – – – – –
– 1 1 – – – –
– 1 1 – – – – –
– 1 1 – – – – –
– 1 1 – – – – –
on CCR
Affect
105