S9S12P128J0MFT Freescale Semiconductor, S9S12P128J0MFT Datasheet - Page 193
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S9S12P128J0MFT
Manufacturer Part Number
S9S12P128J0MFT
Description
MCU 128K FLASH AUTO 48-QFN
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet
1.S9S12P32J0MFT.pdf
(566 pages)
Specifications of S9S12P128J0MFT
Core Processor
HCS12
Core Size
16-Bit
Speed
32MHz
Connectivity
CAN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
34
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
6K x 8
Voltage - Supply (vcc/vdd)
1.72 V ~ 5.5 V
Data Converters
A/D 10x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
48-QFN Exposed Pad
Controller Family/series
S12
No. Of I/o's
34
Ram Memory Size
6KB
Cpu Speed
32MHz
No. Of Timers
1
Rohs Compliant
Yes
Processor Series
S12P
Core
HCS12
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
KIT33812ECUEVME, DEMO9S12PFAME
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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S12SDBGV1 SCR encoding because OR possibilities are very limited in the channel encoding. By adding
OR forks as shown in red this scenario is possible.
On simultaneous matches the lowest channel number has priority so with this configuration the forking
from State1 has the peculiar effect that a simultaneous match0/match1 transitions to final state but a
simultaneous match2/match1transitions to state2.
6.5.9
Trigger when a routine/event at M2 follows either M1 or M0.
Trigger when an event M2 is followed by either event M0 or event M1
Scenario 8a and 8b are possible with the S12SDBGV1 and S12SDBGV2 SCR encoding
Freescale Semiconductor
SCR1=1101
SCR1=0111
SCR1=0010
State1
State1
State1
Scenario 8
M1
M01
M2
SCR2=1100
SCR2=0101
SCR2=0111
State2
State2
State2
S12P-Family Reference Manual, Rev. 1.13
M0
Figure 6-37. Scenario 8a
Figure 6-38. Scenario 8b
Figure 6-36. Scenario 7
M2
M2
M01
M02
Final State
Final State
SCR3=1101
State3
M01
M12
Final State
S12S Debug Module (S12SDBGV2)
193
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