S9S12P128J0MFT Freescale Semiconductor, S9S12P128J0MFT Datasheet - Page 361

• Manufacturer Part Number: S9S12P128J0MFT
• Description: MCU 128K FLASH AUTO 48-QFN
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12P128J0MFT

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 10x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 48-QFN Exposed Pad
• Controller Family/series: S12
• No. Of I/o's: 34
• Ram Memory Size: 6KB
• Cpu Speed: 32MHz
• No. Of Timers: 1
• Rohs Compliant: Yes
• Processor Series: S12P
• Core: HCS12
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: KIT33812ECUEVME, DEMO9S12PFAME
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

When using the 16-bit concatenated mode, the clock source is determined by the low-order 8-bit channel
clock select control bits. That is channel 5 when channels 4 and 5 are concatenated, channel 3 when
channels 2 and 3 are concatenated, and channel 1 when channels 0 and 1 are concatenated. The resulting
PWM is output to the pins of the corresponding low-order 8-bit channel as also shown in
The polarity of the resulting PWM output is controlled by the PPOLx bit of the corresponding low-order
8-bit channel as well.
After concatenated mode is enabled (CONxx bits set in PWMCTL register), enabling/disabling the
corresponding 16-bit PWM channel is controlled by the low-order PWMEx bit. In this case, the high-order
bytes PWMEx bits have no effect and their corresponding PWM output is disabled.
In concatenated mode, writes to the 16-bit counter by using a 16-bit access or writes to either the low or
high-order byte of the counter will reset the 16-bit counter. Reads of the 16-bit counter must be made by
16-bit access to maintain data coherency.
Either left aligned or center aligned output mode can be used in concatenated mode and is controlled by
the low-order CAEx bit. The high-order CAEx bit has no effect.
Freescale Semiconductor
Clock Source 5
Clock Source 3
Clock Source 1
S12P-Family Reference Manual, Rev. 1.13
Figure 10-40. PWM 16-Bit Mode
PWMCNT4
PWMCNT2
PWMCNT0
High
High
High
Period/Duty Compare
Period/Duty Compare
Period/Duty Compare
Pulse-Width Modulator (PWM8B6CV1) Block Description
PWCNT5
PWCNT3
PWCNT1
Low
Low
Low
PWM5
PWM3
PWM1
Figure
10-40.
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