S9S12P128J0MFT Freescale Semiconductor, S9S12P128J0MFT Datasheet - Page 197

• Manufacturer Part Number: S9S12P128J0MFT
• Description: MCU 128K FLASH AUTO 48-QFN
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12P128J0MFT

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 10x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 48-QFN Exposed Pad
• Controller Family/series: S12
• No. Of I/o's: 34
• Ram Memory Size: 6KB
• Cpu Speed: 32MHz
• No. Of Timers: 1
• Rohs Compliant: Yes
• Processor Series: S12P
• Core: HCS12
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: KIT33812ECUEVME, DEMO9S12PFAME
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 7
S12 Clock, Reset and Power Management Unit (S12CPMU)
Revision History
7.1
This specification describes the function of the Clock, Reset and Power Management Unit (S12CPMU).
7.1.1
The Pierce Oscillator (OSCLCP) contains circuitry to dynamically control current gain in the output
amplitude. This ensures a signal with low harmonic distortion, low power and good noise immunity.
Freescale Semiconductor
Number
Version
V01.00
V01.01
V01.02
V01.03
V01.04
V01.05
•
•
•
•
•
The Pierce oscillator (OSCLCP) provides a robust, low-noise and low-power external clock source.
It is designed for optimal start-up margin with typical crystal oscillators.
The Voltage regulator (IVREG) operates from the range 3.13V to 5.5V. It provides all the required
chip internal voltages and voltage monitors.
The Phase Locked Loop (PLL) provides a highly accurate frequency multiplier with internal filter.
The Internal Reference Clock (IRC1M) provides a1MHz clock.
Supports crystals or resonators from 4MHz to 16MHz.
11 Dec. 08 11 Dec. 08
Revision
17 Jun. 09 17 Jun. 09
27 Apr. 10 27 Apr. 10
Introduction
16 Jan.07
9 July 08
7 Oct. 08
Date
Features
Effective
16 Jan. 07
7 Oct. 08
9 July 08
Date
S12P-Family Reference Manual, Rev. 1.13
Author
Initial release
added IRCLK to Block Diagram
clarified and detailed oscillator filter functionality
added note, that startup time of external oscillator t
considered, especially when entering Pseudo Stop Mode
Modified reset phase descriptions to reference f
f
cycles in section: Description of Reset Operation
Major rework fixing typos, figures and tables and improved
description of Adaptive Oscillator Filter.
PLLRST
and correct typo of RESET pin sample point from 64 to 256
Description of Changes
VCORST
UPOSC
instead of
must be
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