S9S12P128J0MFT Freescale Semiconductor, S9S12P128J0MFT Datasheet - Page 347
![no-image](/images/manufacturer_photos/0/2/262/freescale_semiconductor_sml.jpg)
S9S12P128J0MFT
Manufacturer Part Number
S9S12P128J0MFT
Description
MCU 128K FLASH AUTO 48-QFN
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet
1.S9S12P32J0MFT.pdf
(566 pages)
Specifications of S9S12P128J0MFT
Core Processor
HCS12
Core Size
16-Bit
Speed
32MHz
Connectivity
CAN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
34
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
6K x 8
Voltage - Supply (vcc/vdd)
1.72 V ~ 5.5 V
Data Converters
A/D 10x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
48-QFN Exposed Pad
Controller Family/series
S12
No. Of I/o's
34
Ram Memory Size
6KB
Cpu Speed
32MHz
No. Of Timers
1
Rohs Compliant
Yes
Processor Series
S12P
Core
HCS12
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
KIT33812ECUEVME, DEMO9S12PFAME
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Read: anytime
Write: anytime (any value written causes PWM counter to be reset to 0x0000).
10.3.2.13 PWM Channel Period Registers (PWMPERx)
There is a dedicated period register for each channel. The value in this register determines the period of
the associated PWM channel.
The period registers for each channel are double buffered so that if they change while the channel is
enabled, the change will NOT take effect until one of the following occurs:
In this way, the output of the PWM will always be either the old waveform or the new waveform, not some
variation in between. If the channel is not enabled, then writes to the period register will go directly to the
latches as well as the buffer.
Reference
To calculate the output period, take the selected clock source period for the channel of interest (A, B, SA,
or SB) and multiply it by the value in the period register for that channel:
For boundary case programming values, please refer to
Freescale Semiconductor
Module Base + 0x00011
Reset
•
•
•
•
•
•
W
R
The effective period ends
The counter is written (counter resets to 0x0000)
The channel is disabled
Left aligned output (CAEx = 0)
PWMx period = channel clock period * PWMPERx center aligned output (CAEx = 1)
PWMx period = channel clock period * (2 * PWMPERx)
Section 10.4.2.3, “PWM Period and Duty,”
Bit 7
0
0
7
Reads of this register return the most recent value written. Reads do not
necessarily return the value of the currently active period due to the double
buffering scheme.
Figure 10-20. PWM Channel Counter Registers (PWMCNT5)
6
0
0
6
S12P-Family Reference Manual, Rev. 1.13
5
0
0
5
NOTE
4
0
0
4
for more information.
Section 10.4.2.8, “PWM Boundary Cases.”
Pulse-Width Modulator (PWM8B6CV1) Block Description
3
0
0
3
2
0
0
2
1
0
0
1
Bit 0
0
0
0
347
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