S9S12P128J0MFT Freescale Semiconductor, S9S12P128J0MFT Datasheet - Page 272
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S9S12P128J0MFT
Manufacturer Part Number
S9S12P128J0MFT
Description
MCU 128K FLASH AUTO 48-QFN
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet
1.S9S12P32J0MFT.pdf
(566 pages)
Specifications of S9S12P128J0MFT
Core Processor
HCS12
Core Size
16-Bit
Speed
32MHz
Connectivity
CAN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
34
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
6K x 8
Voltage - Supply (vcc/vdd)
1.72 V ~ 5.5 V
Data Converters
A/D 10x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
48-QFN Exposed Pad
Controller Family/series
S12
No. Of I/o's
34
Ram Memory Size
6KB
Cpu Speed
32MHz
No. Of Timers
1
Rohs Compliant
Yes
Processor Series
S12P
Core
HCS12
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
KIT33812ECUEVME, DEMO9S12PFAME
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Freescale’s Scalable Controller Area Network (S12MSCANV3)
1. Read: Only when in sleep mode (SLPRQ = 1 and SLPAK = 1) or initialization mode (INITRQ = 1 and INITAK = 1)
8.3.2.16
This register reflects the status of the MSCAN transmit error counter.
1. Read: Only when in sleep mode (SLPRQ = 1 and SLPAK = 1) or initialization mode (INITRQ = 1 and INITAK = 1)
272
Module Base + 0x000E
Module Base + 0x000F
Write: Unimplemented
Write: Unimplemented
Reset:
Reset:
W
W
R
R
MSCAN Transmit Error Counter (CANTXERR)
RXERR7
TXERR7
Reading this register when in any other mode other than sleep or
initialization mode may return an incorrect value. For MCUs with dual
CPUs, this may result in a CPU fault condition.
Writing to this register when in special modes can alter the MSCAN
functionality.
Reading this register when in any other mode other than sleep or
initialization mode, may return an incorrect value. For MCUs with dual
CPUs, this may result in a CPU fault condition.
Writing to this register when in special modes can alter the MSCAN
functionality.
0
0
7
7
Figure 8-19. MSCAN Transmit Error Counter (CANTXERR)
Figure 8-18. MSCAN Receive Error Counter (CANRXERR)
RXERR6
TXERR6
= Unimplemented
= Unimplemented
0
0
6
6
S12P-Family Reference Manual, Rev. 1.13
RXERR5
TXERR5
0
0
5
5
RXERR4
TXERR4
NOTE
NOTE
0
0
4
4
RXERR3
TXERR3
3
0
3
0
RXERR2
TXERR2
0
0
2
2
Access: User read/write
Access: User read/write
RXERR1
TXERR1
Freescale Semiconductor
0
0
1
1
RXERR0
TXERR0
0
0
0
0
(1)
(1)
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