MC908GT16CBE Freescale Semiconductor, MC908GT16CBE Datasheet - Page 193
![IC MCU 16K FLASH 8MHZ SPI 42SDIP](/photos/12/38/123871/mc908gt16cbe_sml.jpg)
MC908GT16CBE
Manufacturer Part Number
MC908GT16CBE
Description
IC MCU 16K FLASH 8MHZ SPI 42SDIP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MC908GT8CFBE.pdf
(292 pages)
Specifications of MC908GT16CBE
Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
SCI, SPI
Peripherals
LVD, POR, PWM
Number Of I /o
36
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
42-DIP (0.600", 15.24mm)
Controller Family/series
HC08
No. Of I/o's
34
Ram Memory Size
512Byte
Cpu Speed
8MHz
No. Of Timers
2
Embedded Interface Type
I2C, SCI, SPI
Rohs Compliant
Yes
Processor Series
HC08GT
Core
HC08
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
SCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
30
Number Of Timers
4
Operating Supply Voltage
0 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
Development Tools By Supplier
FSICEBASE, DEMO908GZ60E, M68CBL05CE, M68EML08GPGTE
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit, 8 Channel
Package
42SPDIP
Family Name
HC08
Maximum Speed
8 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
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15.7 SIM Registers
The SIM has three memory-mapped registers.
15.7.1 SIM Break Status Register
The SIM break status register (SBSR) contains a flag to indicate that a break caused an exit from wait
mode. This register is only used in emulation mode.
Freescale Semiconductor
CGMXCLK
INT/BREAK
IAB
Note: 1. Writing a 0 clears SBSW.
Address:
Reset:
Note: Previous data can be operand data or the STOP opcode, depending on the last instruction.
Read:
CPUSTOP
Write:
MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0
R/W
IDB
IAB
$FE00
Bit 7
R
R
0
Figure 15-19. Stop Mode Recovery from Interrupt
Address
Figure 15-20. SIM Break Status Register (SBSR)
$FE00
$FE01
$FE03
STOP ADDR
STOP +1
= Reserved
Figure 15-18. Stop Mode Entry Timing
R
6
0
PREVIOUS DATA
Table 15-4. SIM Registers
R
5
0
STOP ADDR + 1
STOP + 2
Table 15-4
Register
STOP RECOVERY PERIOD
SBFCR
SBSR
SRSR
NEXT OPCODE
R
4
0
STOP + 2
shows the mapping of these registers.
R
3
0
SAME
SP
Access Mode
R
2
0
SAME
User
User
User
SP – 1
Note
SBSW
SAME
1
0
(1)
SAME
SP – 2
Bit 0
R
0
SIM Registers
SP – 3
193
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