S912XEP100J5MAG Freescale Semiconductor, S912XEP100J5MAG Datasheet - Page 122

• Manufacturer Part Number: S912XEP100J5MAG
• Description: MCU 64K FLASH 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S912XEP100J5MAG

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 50MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 119
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 24x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1. Read: Always reads 0x00
Chapter 2 Port Integration Module (S12XEPIMV1)
The ECLKCTL register is used to control the availability of the free-running clocks and the free-running
clock divider.
2.3.16
122
Address 0x001D (PRR)
NCLKX2
NECLK
Write: Unimplemented
DIV16
Field
EDIV
Reset
4-0
7
6
5
W
R
No ECLK—Disable ECLK output
This bit controls the availability of a free-running clock on the ECLK pin.
Clock output is always active in emulation modes and if enabled in all other operating modes.
1 ECLK disabled
0 ECLK enabled
No ECLKX2—Disable ECLKX2 output
This bit controls the availability of a free-running clock on the ECLKX2 pin. This clock has a fixed rate of twice the
internal Bus Clock.
Clock output is always active in emulation modes and if enabled in all other operating modes.
1 ECLKX2 disabled
0 ECLKX2 enabled
Free-running ECLK predivider—Divide by 16
This bit enables a divide-by-16 stage on the selected EDIV rate.
1 Divider enabled: ECLK rate = EDIV rate divided by 16
0 Divider disabled: ECLK rate = EDIV rate
Free-running ECLK Divider—Configure ECLK rate
These bits determine the rate of the free-running clock on the ECLK pin. Divider is always disabled in emulation
modes and active as programmed in all other operating modes.
00000 ECLK rate = Bus Clock rate
00001 ECLK rate = Bus Clock rate divided by 2
00010 ECLK rate = Bus Clock rate divided by 3, ...
11111 ECLK rate = Bus Clock rate divided by 32
PIM Reserved Register
0
0
7
= Unimplemented or Reserved
0
0
6
Table 2-16. ECLKCTL Register Field Descriptions
MC9S12XE-Family Reference Manual , Rev. 1.23
Figure 2-14. PIM Reserved Register
0
0
5
0
0
4
Description
3
0
0
0
0
2
Freescale Semiconductor
0
0
1
Access: User read
0
0
0
(1)