S912XEP100J5MAG Freescale Semiconductor, S912XEP100J5MAG Datasheet - Page 717

• Manufacturer Part Number: S912XEP100J5MAG
• Description: MCU 64K FLASH 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S912XEP100J5MAG

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 50MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 119
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 24x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

channel becomes enabled (PWMEx = 1), the associated PWM counter continues from the count in the
PWMCNTx register. This allows the waveform to continue where it left off when the channel is re-
enabled. When the channel is disabled, writing “0” to the period register will cause the counter to reset on
the next selected clock.
Generally, writes to the counter are done prior to enabling a channel in order to start from a known state.
However, writing a counter can also be done while the PWM channel is enabled (counting). The effect is
similar to writing the counter when the channel is disabled, except that the new period is started
immediately with the output set according to the polarity bit.
The counter is cleared at the end of the effective period (see
Section 19.4.2.6, “Center Aligned Outputs”
19.4.2.5
The PWM timer provides the choice of two types of outputs, left aligned or center aligned. They are
selected with the CAEx bits in the PWMCAE register. If the CAEx bit is cleared (CAEx = 0), the
corresponding PWM output will be left aligned.
In left aligned output mode, the 8-bit counter is configured as an up counter only. It compares to two
registers, a duty register and a period register as shown in the block diagram in
PWM counter matches the duty register the output flip-flop changes state causing the PWM waveform to
also change state. A match between the PWM counter and the period register resets the counter and the
output flip-flop, as shown in
duty register to the associated registers, as described in
counter counts from 0 to the value in the period register – 1.
Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
When PWMCNTx register written to
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
Counter Clears ($00)
Effective period ends
any value
Left Aligned Outputs
If the user wants to start a new “clean” PWM waveform without any
“history” from the old waveform, the user must write to channel counter
(PWMCNTx) prior to enabling the PWM channel (PWMEx = 1).
Writing to the counter while the channel is enabled can cause an irregular
PWM cycle to occur.
Changing the PWM output mode from left aligned to center aligned output
(or vice versa) while channels are operating can cause irregularities in the
PWM output. It is recommended to program the output mode before
enabling the PWM channel.
Figure
Table 19-4. PWM Timer Counter Conditions
MC9S12XE-Family Reference Manual Rev. 1.23
19-19, as well as performing a load from the double buffer period and
(PWMEx = 1). Counts from last value in
When PWM channel is enabled
for more details).
Counter Counts
PWMCNTx.
NOTE
NOTE
NOTE
Section 19.4.2.3, “PWM Period and
Section 19.4.2.5, “Left Aligned Outputs”
Chapter 19 Pulse-Width Modulator (S12PWM8B8CV1)
When PWM channel is disabled
Figure
Counter Stops
(PWMEx = 0)
19-19. When the
Duty”. The
and
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