S912XEP100J5MAG Freescale Semiconductor, S912XEP100J5MAG Datasheet - Page 548

• Manufacturer Part Number: S912XEP100J5MAG
• Description: MCU 64K FLASH 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S912XEP100J5MAG

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 50MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 119
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 24x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 14 Enhanced Capture Timer (ECT16B8CV3)
Write used in the flag clearing mechanism. Writing a one to the flag clears the flag. Writing a zero will not
affect the current status of the bit.
All bits reset to zero.
TFLG2 indicates when interrupt conditions have occurred. The flag can be cleared via the normal flag
clearing mechanism (writing a one to the flag) or via the fast flag clearing mechanism (Reference TFFCA
bit in
14.3.2.14 Timer Input Capture/Output Compare Registers 0–7
548
Module Base + 0x0010
Module Base + 0x0011
Module Base + 0x0012
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
Reset
Reset
Reset
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
Field
TOF
7
Section 14.3.2.6, “Timer System Control Register 1
W
W
W
R
R
R
Bit 15
Bit 15
Timer Overflow Flag — Set when 16-bit free-running timer overflows from 0xFFFF to 0x0000.
Bit 7
15
15
0
0
0
7
When TFFCA = 1, the flag cannot be cleared via the normal flag clearing
mechanism (writing a one to the flag). Reference
System Control Register 1
Figure 14-20. Timer Input Capture/Output Compare Register 0 High (TC0)
Figure 14-22. Timer Input Capture/Output Compare Register 1 High (TC1)
Figure 14-21. Timer Input Capture/Output Compare Register 0 Low (TC0)
Bit 14
Bit 14
Bit 6
14
14
0
0
0
6
MC9S12XE-Family Reference Manual Rev. 1.23
Table 14-18. TFLG2 Field Descriptions
Bit 13
Bit 13
Bit 5
13
13
0
5
0
0
(TSCR1)”.
Bit 12
Bit 12
Bit 4
NOTE
12
12
0
0
0
4
Description
(TSCR1)”).
Bit 11
Bit 11
Bit 3
11
11
0
0
0
3
Section 14.3.2.6, “Timer
Bit 10
Bit 10
Bit 2
10
10
0
2
0
0
Freescale Semiconductor
Bit 9
Bit 1
Bit 9
0
0
0
9
1
9
Bit 8
Bit 0
Bit 8
0
0
0
8
0
8