S912XEP100J5MAG Freescale Semiconductor, S912XEP100J5MAG Datasheet - Page 251

• Manufacturer Part Number: S912XEP100J5MAG
• Description: MCU 64K FLASH 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S912XEP100J5MAG

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 50MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 119
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 24x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

5.3.2.2
Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other
modes the data is read from this register.
Write: Anytime. In emulation modes, write operations will also be directed to the external bus.
This register allows programming of two independent values determining the amount of additional stretch
cycles for external accesses (wait states).
With two bits in S12X_MMC register MMCCTL0 for every individual CSx line one of the two counter
options or the EWAIT input is selected as stretch source. The chip select outputs can also be disabled to
free up the pins for alternative functions
descriptions.
If EWAIT input usage is selected in MMCCTL0 the minimum number of stretch cycles is 2 for accesses
to the related address range.
If configured respectively, stretch cycles are added as programmed or dependent on EWAIT in normal
expanded mode and emulation expanded mode; function not available in all other operating modes.
Freescale Semiconductor
Module Base +0x000F (PRR)
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
Reset
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
W
R
External Bus Interface Control Register 1 (EBICTL1)
0
0
7
CSxE1
= Unimplemented or Reserved
Figure 5-4. External Bus Interface Control Register 1 (EBICTL1)
EXSTR12
ASIZ[4:0]
0
0
1
1
00011
10110
10111
11111
1
6
:
:
MC9S12XE-Family Reference Manual Rev. 1.23
CSxE0
Table 5-5. External Address Bus Size
EXSTR11
0
1
0
1
Table 5-6. Chip select function
5
1
(Table
CSx disabled
CSx stretched with EXSTR0
CSx stretched with EXSTR1
CSx stretched with EWAIT
Available External Address Lines
EXSTR10
5-6). Refer also to S12X_MMC section for register bit
1
4
ADDR[21:1], UDS
ADDR[22:1], UDS
ADDR[2:1], UDS
:
Function
0
0
3
Chapter 5 External Bus Interface (S12XEBIV4)
EXSTR02
2
1
EXSTR01
1
1
EXSTR00
1
0
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