DF36054FPJV Renesas Electronics America, DF36054FPJV Datasheet - Page 26

• Manufacturer Part Number: DF36054FPJV
• Description: MCU 3/5V 32K J-TEMP PB-FREE 64-L
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H Tinyr

Specifications of DF36054FPJV

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI, SSU
• Peripherals: PWM, WDT
• Number Of I /o: 45
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Figure 12.36 Input Capture Buffer Operation............................................................................. 221
Figure 12.37 Example of Buffer Operation Setting Procedure................................................... 222
Figure 12.38 Example of Buffer Operation (1)
Figure 12.39 Example of Compare Match Timing for Buffer Operation ................................... 224
Figure 12.40 Example of Buffer Operation (2)
Figure 12.41 Input Capture Timing of Buffer Operation............................................................ 226
Figure 12.42 Buffer Operation (3)
Figure 12.43 Buffer Operation (4)
Figure 12.44 Example of Output Disable Timing of Timer Z by Writing to TOER .................. 229
Figure 12.45 Example of Output Disable Timing of Timer Z by External Trigger.................... 230
Figure 12.46 Example of Output Inverse Timing of Timer Z by Writing to TFCR ................... 230
Figure 12.47 Example of Output Inverse Timing of Timer Z by Writing to POCR................... 231
Figure 12.48 IMF Flag Set Timing when Compare Match Occurs ............................................ 232
Figure 12.49 IMF Flag Set Timing at Input Capture .................................................................. 233
Figure 12.50 OVF Flag Set Timing ............................................................................................ 233
Figure 12.51 Status Flag Clearing Timing.................................................................................. 234
Figure 12.52 Contention between TCNT Write and Clear Operations....................................... 235
Figure 12.53 Contention between TCNT Write and Increment Operations ............................... 236
Figure 12.54 Contention between GR Write and Compare Match............................................. 237
Figure 12.55 Contention between TCNT Write and Overflow................................................... 238
Figure 12.56 Contention between GR Read and Input Capture.................................................. 239
Figure 12.57 Contention between Count Clearing and Increment Operations by Input
Figure 12.58 Contention between GR Write and Input Capture................................................. 241
Figure 12.59 When Compare Match and Bit Manipulation Instruction to TOCR Occur at the
Section 13 Watchdog Timer
Figure 13.1 Block Diagram of Watchdog Timer ........................................................................ 245
Figure 13.2 Watchdog Timer Operation Example...................................................................... 249
Section 14 Serial Communication Interface 3 (SCI3)
Figure 14.1 Block Diagram of SCI3........................................................................................... 253
Figure 14.2 Data Format in Asynchronous Communication ...................................................... 270
Figure 14.3 Relationship between Output Clock and Transfer Data Phase
Figure 14.4 Sample SCI3 Initialization Flowchart ..................................................................... 271
Rev. 4.00 Mar. 15, 2006 Page xxiv of xxxii
(Asynchronous Mode) (Example with 8-Bit Data, Parity, Two Stop Bits) ............. 270
(Buffer Operation for Output Compare Register) ................................................. 223
(Buffer Operation for Input Capture Register) ...................................................... 225
(Buffer Operation in Complementary PWM Mode CMD1 = CMD0 = 1)............ 227
(Buffer Operation in Complementary PWM Mode CMD1 = CMD0 = 1)............ 228
Capture .................................................................................................................. 240
Same Timing ......................................................................................................... 243