DF36054FPJV Renesas Electronics America, DF36054FPJV Datasheet - Page 336
![MCU 3/5V 32K J-TEMP PB-FREE 64-L](/photos/28/61/286100/64-lqfp__plqp0064kb-a_sml.jpg)
DF36054FPJV
Manufacturer Part Number
DF36054FPJV
Description
MCU 3/5V 32K J-TEMP PB-FREE 64-L
Manufacturer
Renesas Electronics America
Series
H8® H8/300H Tinyr
Datasheet
1.DF36057GFZV.pdf
(594 pages)
Specifications of DF36054FPJV
Core Processor
H8/300H
Core Size
16-Bit
Speed
20MHz
Connectivity
CAN, SCI, SSU
Peripherals
PWM, WDT
Number Of I /o
45
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Section 15 Controller Area Network for Tiny (TinyCAN)
15.3.4
GSR indicates the status of the CAN bus. Each bit in GSR is set or cleared to notify the CPU of
the TinyCAN status.
Rev. 4.00 Mar. 15, 2006 Page 302 of 556
REJ09B0026-0400
Bit
7, 6
5
4
3
Bit Name
—
ERPS
HALT
RESET
General Status Register (GSR)
Initial
Value
All 0
0
0
1
R/W
—
R
R
R
Description
Reserved
These bits are always read as 0.
Error Passive Status Flag
Indicates whether the CDLC is in the error-passive state.
This flag is always set to 1 when the CDLC is in the error-
passive state or bus off state.
[Setting condition]
When TEC
[Clearing condition]
When the error-active state is entered
Indicates whether the TinyCAN is in halt mode.
[Setting condition]
When the CAN bus receives an intermission frame or the
bus is idle with the HLTRQ bit in MCR set to 1
[Clearing condition]
When the HLTRQ bit is cleared to 0 and halt mode is
exited
Reset Status Flag
Indicates whether the TinyCAN is in reset mode.
[Setting condition]
When the TinyCAN is in the reset state
[Clearing condition]
When communication with the CAN bus is enabled after
the reset procedure completes
Halt Status Flag
128 or REC
128
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