DF36054FPJV Renesas Electronics America, DF36054FPJV Datasheet - Page 428
![MCU 3/5V 32K J-TEMP PB-FREE 64-L](/photos/28/61/286100/64-lqfp__plqp0064kb-a_sml.jpg)
DF36054FPJV
Manufacturer Part Number
DF36054FPJV
Description
MCU 3/5V 32K J-TEMP PB-FREE 64-L
Manufacturer
Renesas Electronics America
Series
H8® H8/300H Tinyr
Datasheet
1.DF36057GFZV.pdf
(594 pages)
Specifications of DF36054FPJV
Core Processor
H8/300H
Core Size
16-Bit
Speed
20MHz
Connectivity
CAN, SCI, SSU
Peripherals
PWM, WDT
Number Of I /o
45
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
- Current page: 428 of 594
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Section 18 A/D Converter
18.3
The A/D converter has the following registers.
18.3.1
There are four 16-bit read-only ADDR registers; ADDRA to ADDRD, used to store the results of
A/D conversion. The ADDR registers, which store a conversion result for each analog input
channel, are shown in table 18.2.
The converted 10-bit data is stored in bits 15 to 6. The lower 6 bits are always read as 0.
The data bus width between the CPU and the A/D converter is 8 bits. The upper byte can be read
directly from the CPU, however the lower byte should be read via a temporary register. The
temporary register contents are transferred from the ADDR when the upper byte data is read.
Therefore, byte access to ADDR should be done by reading the upper byte first then the lower
one. Word access is also possible. ADDR is initialized to H'0000.
Table 18.2 Analog Input Channels and Corresponding ADDR Registers
Rev. 4.00 Mar. 15, 2006 Page 394 of 556
REJ09B0026-0400
Group 0
AN0
AN1
AN2
AN3
Analog Input Channel
A/D data register A (ADDRA)
A/D data register B (ADDRB)
A/D data register C (ADDRC)
A/D data register D (ADDRD)
A/D control/status register (ADCSR)
A/D control register (ADCR)
Register Descriptions
A/D Data Registers A to D (ADDRA to ADDRD)
Group 1
AN4
AN5
AN6
AN7
A/D Data Register to be Stored Results of A/D Conversion
ADDRA
ADDRB
ADDRC
ADDRD
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