DF36054FPJV Renesas Electronics America, DF36054FPJV Datasheet - Page 408

• Manufacturer Part Number: DF36054FPJV
• Description: MCU 3/5V 32K J-TEMP PB-FREE 64-L
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H Tinyr

Specifications of DF36054FPJV

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI, SSU
• Peripherals: PWM, WDT
• Number Of I /o: 45
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 16 Synchronous Serial Communication Unit (SSU)
16.4.9
Serial Data Reception
Figure 16.12 shows an example of the SSU operation for reception. In serial reception, the SSU
operates as described below.
When the SSU is set as a master device, it outputs a synchronous clock and inputs data. When the
SSU is set as a slave device, the SCS pin is in the low-input state and inputs data in synchronized
with the input clock. When the SSU is set as a master device, it outputs a receive clock and starts
reception by performing dummy read on SSRDR.
After eight bits of data is received, the RDRF bit in SSSR is set to 1 and received data is stored in
SSRDR. If the RIE bit in SSER is set to 1 at this time, an RXI is generated. If SSRDR is read, the
RDRF bit is automatically cleared to 0.
When the SSU is set as a master device and reception is ended, received data is read after setting
the RSSTP bit in SSER to 1. Then the SSU outputs eight bits of clocks and operation is stopped.
After that, the RE and RSSTP bits are cleared to 0 and the last received data is read. Note that if
SSRDR is read while the RE bit is set to 1, received clock is output again.
When the eighth clock rises while the RDRF bit is 1, the ORER bit in SSSR is set. Then an
overrun error (OEI) is generated and operation is stopped. When the ORER bit in SSSR is set to 1,
reception cannot be performed. Therefore confirm that the ORER bit is cleared to 0 before
reception.
The set timings of the RDRF and ORER flags differ according to the CPHS setting. These timings
are shown in figure 16.2. When the CPHS bit is set to 1, the flag is set during the frame. Therefore
care should be taken at the end of reception.
The sample flowchart for serial data reception is the same as that in clocked synchronous
communication mode.
Rev. 4.00 Mar. 15, 2006 Page 374 of 556
REJ09B0026-0400