MC9S12DP512CPVER Freescale Semiconductor, MC9S12DP512CPVER Datasheet - Page 90

IC MCU 16BIT 4K FLASH 112-LQFP

MC9S12DP512CPVER

Manufacturer Part Number
MC9S12DP512CPVER
Description
IC MCU 16BIT 4K FLASH 112-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet

Specifications of MC9S12DP512CPVER

Core Processor
HCS12
Core Size
16-Bit
Speed
25MHz
Connectivity
CAN, I²C, SCI, SPI
Peripherals
PWM, WDT
Number Of I /o
91
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 5.25 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
Package
112LQFP
Family Name
HCS12
Maximum Speed
25 MHz
Operating Supply Voltage
2.5|5 V
Data Bus Width
16 Bit
Interface Type
CAN/I2C/SCI/SPI
On-chip Adc
2(8-chx10-bit)
Number Of Timers
8
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
MC9S12DP512CPVERTR

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC9S12DP512CPVER
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
MC9S12DP512 Device Guide V01.25
The total power dissipation can be calculated from:
Two cases with internal voltage regulator enabled and disabled must be considered:
T J
T A
P D
P
INT
JA
1. Internal Voltage Regulator disabled
2. Internal voltage regulator enabled
P
For R
respectively
I
additionally contains the current flowing into the external loads with output high.
P
=
DDR
=
=
IO
IO
=
Junction Temperature, [ C
Ambient Temperature, [ C
=
Total Chip Power Dissipation, [W]
is the sum of all output currents on I/O ports associated with VDDX and VDDR.
is the sum of all output currents on I/O ports associated with VDDX and VDDR.
Package Thermal Resistance, [ C/W]
is the current shown in Table A-7 and not the overall current flowing into VDDR, which
DSON
Chip Internal Power Dissipation, [W]
is valid:
P INT
R DSON
=
I DD V DD
P INT
R DSON
=
P IO
P IO
=
V DD5 V OH
----------------------------------- - for outputs driven high
T J
I DDR V DDR
=
P D
+
=
=
=
I OH
V OL
----------- - for outputs driven low
I DDPLL V DDPLL
I OL
T A
=
i
i
P INT
;
R DSON
R DSON
+
P D
;
+
+
P IO
I DDA V DDA
JA
I IO
I IO
i
i
2
2
+
I DDA
V DDA

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