R4F24569NVFQV Renesas Electronics America, R4F24569NVFQV Datasheet - Page 276

• Manufacturer Part Number: R4F24569NVFQV
• Description: MCU 256KB FLASH 64K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24569NVFQV

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 6 Bus Controller (BSC)
A setting can be made in bits RCW1 and RCW0 in REFCR to delay RAS signal output by one to
three cycles. Use bits RLW1 and RLW0 in REFCR to adjust the width of the RAS signal. The
settings of bits RCW1, RCW0, RLW1, and RLW0 are valid only in refresh operations.
Figure 6.49 shows the timing when bits RCW1 and RCW0 are set.
Depending on the DRAM used, modification of the WE signal may not be permitted during the
refresh period. In this case, the CBRM bit in REFCR should be set to 1. The bus controller will
then insert refresh cycles in appropriate breaks between bus cycles. Figure 6.50 shows an example
of the timing when the CBRM bit is set to 1. In this case the CS signal is not controlled, and
retains its value prior to the start of the refresh period.
Page 246 of 1392
CSn (RASn)
φ
UCAS, CAS
T
Rp
(RCW1 = 0, RCW0 = 1, RLW1 = 0, RLW0 = 0)
Figure 6.49 CBR Refresh Timing
T
Rrw
T
Rr
T
H8S/2456, H8S/2456R, H8S/2454 Group
Rc1
REJ09B0467-0350 Rev. 3.50
T
Rc2
Jul 07, 2010