R4F24569NVFQV Renesas Electronics America, R4F24569NVFQV Datasheet - Page 906

• Manufacturer Part Number: R4F24569NVFQV
• Description: MCU 256KB FLASH 64K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24569NVFQV

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 15 Serial Communication Interface (SCI, IrDA)
Page 876 of 1392
Bit
4
3
Bit Name
FER
PER
0
0
Initial Value
R/W
R/(W) *
R/(W) *
Description
Framing Error
Indicates that a framing error occurred while
receiving in asynchronous mode and the reception
has ended abnormally.
[Setting condition]
•
[Clearing condition]
•
Parity Error
Indicates that a parity error occurred while
receiving in asynchronous mode and the reception
has ended abnormally.
[Setting condition]
•
[Clearing condition]
•
When the stop bit is 0
In 2-stop-bit mode, only the first stop bit is
checked for a value of 0; the second stop bit is
not checked. If a framing error occurs, the
receive data is transferred to RDR but the
RDRF flag is not set. Also, subsequent serial
reception cannot be continued while the FER
flag is set to 1. In clocked synchronous mode,
serial transmission cannot be continued,
either.
When 0 is written to FER after reading FER =
1
The FER flag is not affected and retains its
previous state when the RE bit in SCR is
cleared to 0.
When a parity error is detected during
reception
If a parity error occurs, the receive data is
transferred to RDR but the RDRF flag is not
set. Also, subsequent serial reception cannot
be continued while the PER flag is set to 1. In
clocked synchronous mode, serial
transmission cannot be continued, either.
When 0 is written to PER after reading PER =
1
The PER flag is not affected and retains its
previous state when the RE bit in SCR is
cleared to 0.
H8S/2456, H8S/2456R, H8S/2454 Group
REJ09B0467-0350 Rev. 3.50
Jul 07, 2010