R4F24569NVFQV Renesas Electronics America, R4F24569NVFQV Datasheet - Page 316

• Manufacturer Part Number: R4F24569NVFQV
• Description: MCU 256KB FLASH 64K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24569NVFQV

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 6 Bus Controller (BSC)
(2) Read Data Extension
If the CKSPE bit is set to 1 in DRACCR when the continuous synchronous DRAM space is read-
accessed in DMAC/EXDMAC single address mode, the establishment time for the read data can
be extended by clock suspend mode. The number of states for insertion of the read data extension
cycle (Tsp) is set in bits RDXC1 and RDXC0 in DRACCR. Be sure to set the OEE bit to 1 in
DRAMCR when the read data will be extended. The extension of the read data is not in
accordance with the bits DDS and EDDS.
Figure 6.74 shows the timing chart when the read data is extended by two cycles.
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Figure 6.74 Example of Timing when the Read Data Is Extended by Two States
(DDS = 1, or EDDS = 1, RDXC1 = 0, RDXC0 = 1, CAS Latency 2)
DACK or EDACK
Precharge-sel
DQMU, DQML
Address bus
SDRAMφ
Data bus
CKE
CAS
RAS
WE
φ
PALL ACTV
address
Column
T
p
address
address
Row
Row
T
r
READ
T
c1
T
cl
NOP
T
c2
Column address
H8S/2456, H8S/2456R, H8S/2454 Group
T
sp1
T
sp2
REJ09B0467-0350 Rev. 3.50
Jul 07, 2010