R4F24569NVFQV Renesas Electronics America, R4F24569NVFQV Datasheet - Page 704

MCU 256KB FLASH 64K 144-LQFP

R4F24569NVFQV

Manufacturer Part Number
R4F24569NVFQV
Description
MCU 256KB FLASH 64K 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2400r
Datasheets

Specifications of R4F24569NVFQV

Core Processor
H8S/2600
Core Size
16/32-Bit
Speed
32MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART, USB
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R4F24569NVFQV
Manufacturer:
Renesas Electronics America
Quantity:
135
Part Number:
R4F24569NVFQV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 10 I/O Ports
• PG2/CS2/ RAS2/RAS*
Note:
• PG1/CS1, PG0/CS0
[Legend]
n = 1 or 0
Page 674 of 1392
Operating
mode
EXPE
CS2E
RMTS2 to
RMTS0
PG2DDR
Pin function PG2
Operating
mode
EXPE
CSnE
PGnDDR
Pin
function
The pin function is switched as shown below according to the combination of the operating
mode, bits RMTS2 to RMTS0 in DRAMCR of the bus controller, bit CS2E in PFCR0, and bit
PG2DDR.
The pin function is switched as shown below according to the combination of the operating
mode, bit CSnE in PFCR0, and bit PGnDDR.
*
input
0
Not supported in the H8S/2456 Group and H8S/2454 Group.
0
output
input
PGn
PG2
1
0
normal space
input
PG2
Area 2 is in
0
0
output
PGn
output
CS2
1
1
1, 2, 4
1, 2, 4
and areas 2 to 5
DRAM space
DRAM space
synchronous
Area 2 is in
output
RAS2
input
are in
PGn
1
0
1
Areas 2 to 5 are
DRAM* space
output
synchronous
CSn
output
RAS*
1
in
input
PGn
input
PG2
0
0
0
output
PG2
0
1
output
PGn
1
input
PG2
0
0
output
PG2
input
PGn
1
H8S/2456, H8S/2456R, H8S/2454 Group
0
normal space
input
PG2
Area 2 is in
0
0
7
7
output
PGn
output
CS2
REJ09B0467-0350 Rev. 3.50
1
1
1
and areas 2 to 5
1
DRAM space
DRAM space
synchronous
Area 2 is in
output
RAS2
are in
input
PGn
1
0
Jul 07, 2010
1
DRAM space
synchronous
Areas 2 to 5
output
CSn
output
RAS*
are in
1

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