M30290FAHP#U5A Renesas Electronics America, M30290FAHP#U5A Datasheet - Page 189

• Manufacturer Part Number: M30290FAHP#U5A
• Description: IC M16C/29 MCU FLASH 96K 80LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/Tiny/29r

Specifications of M30290FAHP#U5A

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 71
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 27x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 80-LQFP
• For Use With: R0K330290S000BE - KIT EVAL STARTER FOR M16C/29M30290T2-CPE - EMULATOR COMPACT M16C/26A/28/29M30290T2-CPE-HP - EMULATOR COMPACT FOR M16C/TINY
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R
R
M
e
E
1
. v
J
6
0
Figure 13.22 Single-phase Waveform Output Mode
1
C
9
1 .
B
2 /
0
2
9
1
M
0
G
(1) Free-running operation
(2) The base timer is reset when the base timer matches either following register
1
r a
0 -
o r
3 .
The above applies under the following conditions.
(The RST4, RST2, and RST1 bits in the G1BCR0 and G1BCR1 registers are set to 0)
(a) G1PO0
(b) G1BTRR (enabled by setting bit RST4 to 1, and bits RST2 and RST1 to 0)
1
u
, 0
The above applies under the following conditions.
1
p
Base timer
G1IRj bit
2
-The IVL bit in the G1POCRj register is set to 0 ("L" output as a default value) and the INV bit is set to 0
-Bits UD1 to UD0 are set to 00
OUTC1j pin
Base timer
OUTC1j pin
G1IRj bit
(not inversed).
-The IVL bit in the G1POCRj register is set to 0 ("L" output as a default value) and the INV
-Bits UD1 to UD0 are set to 00
2
bit is set to 0 (not inversed).
0
0
7
page 163
j=0 to 7
m : Setting value of the G1POj register
G1IRj bit : Bits in the G1IR register
j=1 to 7
m : Setting value of the G1POj register
G1IRj bit : Bits in the G1IR register
n: Setting value of either G1PO0 register or G1BTRR register
(enabled by setting bit RST1 to 1, and bits RST4 and RST2 to 0), or
FFFF
0000
FFFF
0000
16
n+2
16
m
m
16
16
f o
4
5
f
8
m
BT1
f
m
BT1
2
2
(counter increment mode).
(counter increment mode).
Inverse
65536
Inverse
n+2-m
n+2
f
f
BT1
65536-m
BT1
f
BT1
f
When setting to 0,
write 0 by program
BT1
Write 0 by program
if setting to 0
Return to default output level
Inverse
Inverse
Return to default
output level
Inverse