M30290FAHP#U5A Renesas Electronics America, M30290FAHP#U5A Datasheet - Page 230

• Manufacturer Part Number: M30290FAHP#U5A
• Description: IC M16C/29 MCU FLASH 96K 80LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/Tiny/29r

Specifications of M30290FAHP#U5A

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 71
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 27x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 80-LQFP
• For Use With: R0K330290S000BE - KIT EVAL STARTER FOR M16C/29M30290T2-CPE - EMULATOR COMPACT M16C/26A/28/29M30290T2-CPE-HP - EMULATOR COMPACT FOR M16C/TINY
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

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14.1.3.4 Transfer Clock
14.1.3.5 SDA Output
14.1.3.6 SDA Input
9
1
M
Data is transmitted/received using a transfer clock like the one shown in Figure 14.25.
The CSC bit in the U2SMR2 register is used to synchronize the internally generated clock (internal
SCL2) and an external clock supplied to the SCL
synchronization enabled), if a falling edge on the SCL
the internal SCL
ing in the low-level interval. If the internal SCL
low, counting stops, and when the SCL
In this way, the UART2 transfer clock is comprised of the logical product of the internal SCL
pin signal. The transfer clock works from a half period before the falling edge of the internal SCL
bit to the rising edge of the 9
The SWC bit in the U2SMR2 register allows to select whether the SCL
from low-level output at the falling edge of the 9th clock pulse.
If the SCLHI bit in the U2SMR4 register is set to 1 (enabled), SCL
high-impedance state) when a stop condition is detected.
Setting the SWC2 bit in the U2SMR2 register is set to 1 (0 output) makes it possible to forcibly output
a low-level signal from the SCL
(transfer clock) allows the transfer clock to be output from or supplied to the SCL
outputting a low-level signal.
If the SWC9 bit in the U2SMR4 register is set to 1 (SCL
U2SMR3 register is set to 1, the SCL
pulse next to the ninth. Setting the SWC9 bit to 0 (SCL
low-level output.
The data written to the bit 7 to bit 0 (D
with D
The initial value of SDA
SMD2 to SMD0 in the U2MR register is set to 000
Bits DL2 to DL0 in the U2SMR3 register allow to add no delays or a delay of 2 to 8 U2BRG count
source clock cycles to SDA
Setting the SDHI bit in the U2SMR2 register to 1 (SDA
in the high-impedance state. Do not write to the SDHI bit synchronously with the rising edge of the
UART2 transfer clock. This is because the ABT bit may inadvertently be set to 1 (detected).
When the IICM2 bit is set to 0, the 1st to 8th bits (D
0 in the U2RB register. The 9th bit (D
When the IICM2 bit is set to 1, the 1st to 7th bits (D
to bit 0 in the U2RB register and the 8th bit (D
the IICM2 bit is set to 1, providing the CKPH bit is set to 1, the same data as when the IICM2 bit is set
to 0 can be read out by reading the U2RB register after the rising edge of the corresponding clock
pulse of 9th bit.
0
G
1
r a
o r
0 -
3 .
1
u
, 0
1
p
7
2
. The ninth bit (D
2
0
0
7
page 204
2
goes low, at which time the U2BRG register value is reloaded with and starts count-
2
8
transmit output can only be set when IICM is set to 1 (I
f o
) is ACK or NACK.
4
2
5
th
output.
8
bit. To use this function, select an internal clock for the transfer clock.
2
pin even while sending or receiving data. Clearing the SWC2 bit to 0
8
2
7
) is ACK or NACK.
2
pin is fixed to low-level output at the falling edge of the clock
to D
pin goes high, counting restarts.
0
) in the U2TB register is sequentially output beginning
0
2
) is stored in the bit 8 in the U2RB register. Even when
changes state from low to high while the SCL
2
2
7
7
pin. In cases when the CSC bit is set to 1 (clock
(serial I/O disabled).
to D
to D
2
2
pin is detected while the internal SCL
2
output disabled) forcibly places the SDA
2
1
0
hold low enabled) when the CKPH bit in the
) in the received data are stored in the bit 6
hold low disabled) frees the SCL
) in the received data are stored in bits 7 to
2
output is turned off (placed in the
2
pin should be fixed to or freed
2
C bus mode) and bits
2
pin, instead of
2
2
and SCL
2
pin from
is high,
2
pin is
2
2
1st
pin
2