D12350F20IV Renesas Electronics America, D12350F20IV Datasheet - Page 17

• Manufacturer Part Number: D12350F20IV
• Description: IC H8S/2350 MCU 4.5/5.5V 0+K I-T
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of D12350F20IV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 87
• Program Memory Type: ROMless
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Item
B.1 Addresses
B.2 Functions
Page
812
813
821
842
Revision (See Manual for Details)
Table amended
Table amended
Figure amended
TIOR3L H'FE83 TPU3
Figure amended
ABWCR H'FED0 Bus Controller
Address
(low)
H'FF98
Address
(low)
H'FF70
H'FF71
H'FF72
H'FF73
H'FF74
H'FF76
H'FF77
Note: When TGRC or TGRD is designated for buffer operation, this setting is invalid and the register operates as a buffer register.
Bit
Modes 1 to 3, 5 to 7
Initial value
R/W
Register
Name
ADCSR
Legend: *: Don’t care
Notes:
TGR3D I/O Control
Register
Name
PAPCR *
PBPCR *
PCPCR *
PDPCR *
PEPCR *
P3ODR *
PAODR *
0
1
0
1
0
1
:
:
:
1. When bits TPSC2 to TPSC0 in TCR4 are set to B'000 and /1 is used as the TCNT4 count clock,
2. When the BFB bit in TMDR3 is set to 1 and TGR3D is used as a buffer register, this setting is invalid
0
1
0
1
0
1
*
this setting is invalid and input capture is not generated.
and input capture/output compare is not generated.
Bit 7
ADF
ABW7
0
1
0
1
0
1
0
1
0
1
*
*
2
2
2
2
2
2
2
R/W
TGR3D
is output
compare
register
TGR3D
is input
capture
register *
7
1
Bit 6
ADIE
2
Output disabled
Initial output is 0
output
Output disabled
Initial output is 1
output
Capture input
source is
TIOCD3 pin
Capture input
source is channel
4/count clock
Rev. 3.00 Sep 15, 2006 page xv of xxxiv
Bit 5
ADST
1 output at compare match
Toggle output at compare match
1 output at compare match
Toggle output at compare match
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
0 output at compare match
0 output at compare match
Input capture at TCNT4 count-up/
count-down *
Bit 4
SCAN
1
CKS
Bit 3
Bit 2
CH2
Bit 1
CH1
Bit 0
CH0