D12350F20IV Renesas Electronics America, D12350F20IV Datasheet - Page 23

• Manufacturer Part Number: D12350F20IV
• Description: IC H8S/2350 MCU 4.5/5.5V 0+K I-T
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of D12350F20IV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 87
• Program Memory Type: ROMless
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

4.7
Section 5 Interrupt Controller
5.1
5.2
5.3
5.4
5.5
5.6
Section 6 Bus Controller
6.1
6.2
Notes on Use of the Stack ................................................................................................. 89
Overview........................................................................................................................... 91
5.1.1
5.1.2
5.1.3
5.1.4
Register Descriptions ........................................................................................................ 94
5.2.1
5.2.2
5.2.3
5.2.4
5.2.5
Interrupt Sources ............................................................................................................... 99
5.3.1
5.3.2
5.3.3
Interrupt Operation............................................................................................................ 105
5.4.1
5.4.2
5.4.3
5.4.4
5.4.5
Usage Notes ...................................................................................................................... 115
5.5.1
5.5.2
5.5.3
5.5.4
DTC and DMAC Activation by Interrupt.......................................................................... 117
5.6.1
5.6.2
5.6.3
Overview........................................................................................................................... 121
6.1.1
6.1.2
6.1.3
6.1.4
Register Descriptions ........................................................................................................ 126
Features................................................................................................................ 91
Block Diagram ..................................................................................................... 92
Pin Configuration................................................................................................. 93
Register Configuration ......................................................................................... 93
System Control Register (SYSCR) ...................................................................... 94
Interrupt Priority Registers A to K (IPRA to IPRK) ............................................ 95
IRQ Enable Register (IER) .................................................................................. 96
IRQ Sense Control Registers H and L (ISCRH, ISCRL) ..................................... 97
IRQ Status Register (ISR) .................................................................................... 98
External Interrupts................................................................................................ 99
Internal Interrupts................................................................................................. 101
Interrupt Exception Handling Vector Table......................................................... 101
Interrupt Control Modes and Interrupt Operation ................................................ 105
Interrupt Control Mode 0 ..................................................................................... 109
Interrupt Control Mode 2 ..................................................................................... 111
Interrupt Exception Handling Sequence............................................................... 113
Interrupt Response Times .................................................................................... 114
Contention between Interrupt Generation and Disabling ..................................... 115
Instructions That Disable Interrupts..................................................................... 116
Times when Interrupts Are Disabled.................................................................... 116
Interrupts during Execution of EEPMOV Instruction.......................................... 117
Overview.............................................................................................................. 117
Block Diagram ..................................................................................................... 118
Operation ............................................................................................................. 119
Features................................................................................................................ 121
Block Diagram ..................................................................................................... 123
Pin Configuration................................................................................................. 124
Register Configuration ......................................................................................... 125
.................................................................................................... 121
.......................................................................................... 91
Rev. 3.00 Sep 15, 2006 page xxi of xxxiv