D12350F20IV Renesas Electronics America, D12350F20IV Datasheet - Page 275
D12350F20IV
Manufacturer Part Number
D12350F20IV
Description
IC H8S/2350 MCU 4.5/5.5V 0+K I-T
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Specifications of D12350F20IV
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
87
Program Memory Type
ROMless
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
128-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
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Quantity
Price
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Part Number:
D12350F20IV
Manufacturer:
INF
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7.5.3
Idle mode can be specified by setting the RPE bit and DTIE bit in DMACR to 1. In idle mode, one
byte or word is transferred in response to a single transfer request, and this is executed the number
of times specified in ETCR.
One address is specified by MAR, and the other by IOAR. The transfer direction can be specified
by the DTDIR bit in DMACR.
Table 7.7 summarizes register functions in idle mode.
Table 7.7
Legend:
MAR:
IOAR: I/O address register
ETCR: Transfer count register
DTDIR: Data transfer direction bit
MAR specifies the start address of the transfer source or transfer destination as 24 bits. MAR is
neither incremented nor decremented each time a byte or word is transferred.
IOAR specifies the lower 16 bits of the other address. The 8 bits above IOAR have a value of
H'FF.
Register
23
23
H'FF
Memory address register
15
15
Idle Mode
Register Functions in Idle Mode
MAR
ETCR
IOAR
0
0
0
DTDIR = 0
Source
address
register
Destination
address
register
Transfer counter
Function
DTDIR = 1
Destination
address
register
Source
address
register
Rev. 3.00 Sep 15, 2006 page 239 of 988
Initial Setting
Start address of
transfer destination
or transfer source
Start address of
transfer source or
transfer destination
Number of transfers
Section 7 DMA Controller (DMAC)
REJ09B0330-0300
Operation
Fixed
Fixed
Decremented
every transfer;
transfer ends
when count
reaches H'0000
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