MC9S12XDT256MAA Freescale Semiconductor, MC9S12XDT256MAA Datasheet - Page 189
MC9S12XDT256MAA
Manufacturer Part Number
MC9S12XDT256MAA
Description
IC MCU 256K FLASH 80-QFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet
1.MC9S12XD64CAA.pdf
(1348 pages)
Specifications of MC9S12XDT256MAA
Core Processor
HCS12X
Core Size
16-Bit
Speed
80MHz
Connectivity
CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
59
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
80-QFP
Cpu Family
HCS12
Device Core Size
16b
Frequency (max)
40MHz
Interface Type
CAN/I2C/SCI/SPI
Total Internal Ram Size
16KB
# I/os (max)
59
Number Of Timers - General Purpose
12
Operating Supply Voltage (typ)
2.5/5V
Operating Supply Voltage (max)
2.75/5.5V
Operating Supply Voltage (min)
2.35/3.15V
On-chip Adc
8-chx10-bit
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
80
Package Type
PQFP
Processor Series
S12XD
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
16 KB
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
59
Number Of Timers
12
Operating Supply Voltage
0 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
EVB9S12XDP512E
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC9S12XDT256MAA
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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6.3.1.1
All module level switches and flags are located in the module control register
Read: Anytime
Write: Anytime
Freescale Semiconductor
Reset
XGDBGM
XGFRZM
XGSSM
XGEM
Field
W
R
15
14
13
12
XGEM
15
0
0
XGE Mask — This bit controls the write access to the XGE bit. The XGE bit can only be set or cleared if a "1" is
written to the XGEM bit in the same register access.
Read:
Write:
0 Disable write access to the XGE in the same bus cycle
1 Enable write access to the XGE in the same bus cycle
XGFRZ Mask — This bit controls the write access to the XGFRZ bit. The XGFRZ bit can only be set or cleared
if a "1" is written to the XGFRZM bit in the same register access.
Read:
Write:
0 Disable write access to the XGFRZ in the same bus cycle
1 Enable write access to the XGFRZ in the same bus cycle
XGDBG Mask — This bit controls the write access to the XGDBG bit. The XGDBG bit can only be set or cleared
if a "1" is written to the XGDBGM bit in the same register access.
Read:
Write:
0 Disable write access to the XGDBG in the same bus cycle
1 Enable write access to the XGDBG in the same bus cycle
XGSS Mask — This bit controls the write access to the XGSS bit. The XGSS bit can only be set or cleared if a
"1" is written to the XGSSM bit in the same register access.
Read:
Write:
0 Disable write access to the XGSS in the same bus cycle
1 Enable write access to the XGSS in the same bus cycle
FRZM
XGATE Control Register (XGMCTL)
XG
14
0
0
This bit will always read "0".
This bit will always read "0".
This bit will always read "0".
This bit will always read "0".
= Unimplemented or Reserved
DBGM
XG
13
0
0
SSM
XG
12
Table 6-1. XGMCTL Field Descriptions (Sheet 1 of 3)
0
0
Figure 6-3. XGATE Control Register (XGMCTL)
FACTM
XG
11
0
0
MC9S12XDP512 Data Sheet, Rev. 2.21
10
0
0
SWEIFM
XG
0
0
9
XGIEM
0
0
8
Description
XGE XGFRZ XGDBG XGSS XGFACT
7
0
0
6
0
5
0
4
Figure
Chapter 6 XGATE (S12XGATEV2)
0
3
6-3.
2
0
0
SWEIF
XG
0
1
XGIE
0
0
189
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