MC9S12XDT256MAA Freescale Semiconductor, MC9S12XDT256MAA Datasheet - Page 438

IC MCU 256K FLASH 80-QFP

MC9S12XDT256MAA

Manufacturer Part Number
MC9S12XDT256MAA
Description
IC MCU 256K FLASH 80-QFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet

Specifications of MC9S12XDT256MAA

Core Processor
HCS12X
Core Size
16-Bit
Speed
80MHz
Connectivity
CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
59
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
80-QFP
Cpu Family
HCS12
Device Core Size
16b
Frequency (max)
40MHz
Interface Type
CAN/I2C/SCI/SPI
Total Internal Ram Size
16KB
# I/os (max)
59
Number Of Timers - General Purpose
12
Operating Supply Voltage (typ)
2.5/5V
Operating Supply Voltage (max)
2.75/5.5V
Operating Supply Voltage (min)
2.35/3.15V
On-chip Adc
8-chx10-bit
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
80
Package Type
PQFP
Processor Series
S12XD
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
16 KB
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
59
Number Of Timers
12
Operating Supply Voltage
0 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
EVB9S12XDP512E
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3)
Read: Anytime
Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1), except bits IDHITx, which are
read-only
The IDHITx indicators are always related to the message in the foreground buffer (RxFG). When a
message gets shifted into the foreground buffer of the receiver FIFO the indicators are updated as well.
10.3.2.13 MSCAN Reserved Register
This register is reserved for factory testing of the MSCAN module and is not available in normal system
operation modes.
438
IDHIT[2:0]
IDAM[1:0]
Field
5:4
2:0
Identifier Acceptance Mode — The CPU sets these flags to define the identifier acceptance filter organization
(see
mode, no message is accepted such that the foreground buffer is never reloaded.
Identifier Acceptance Hit Indicator — The MSCAN sets these flags to indicate an identifier acceptance hit (see
Section 10.4.3, “Identifier Acceptance
IDHIT2
IDAM1
Section 10.4.3, “Identifier Acceptance
0
0
1
1
0
0
0
0
1
1
1
1
Table 10-16. CANIDAC Register Field Descriptions
Table 10-17. Identifier Acceptance Mode Settings
Table 10-18. Identifier Acceptance Hit Indication
IDHIT1
IDAM0
0
1
0
1
0
0
1
1
0
0
1
1
MC9S12XDP512 Data Sheet, Rev. 2.21
Filter”).
IDHIT0
Filter”).
0
1
0
1
0
1
0
1
Table 10-18
Description
Table 10-17
Identifier Acceptance Mode
Four 16-bit acceptance filters
Two 32-bit acceptance filters
Eight 8-bit acceptance filters
summarizes the different settings.
Filter closed
Identifier Acceptance Hit
summarizes the different settings. In filter closed
Filter 0 hit
Filter 1 hit
Filter 2 hit
Filter 3 hit
Filter 4 hit
Filter 5 hit
Filter 6 hit
Filter 7 hit
Freescale Semiconductor

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