DF3048BVX25WV Renesas Electronics America, DF3048BVX25WV Datasheet - Page 256
![MCU 3/5V 128K PB-FREE 100-TQFP](/photos/28/61/286123/100-tqfp__100-vqfp_sml.jpg)
DF3048BVX25WV
Manufacturer Part Number
DF3048BVX25WV
Description
MCU 3/5V 128K PB-FREE 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Specifications of DF3048BVX25WV
Core Processor
H8/300H
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, PWM, WDT
Number Of I /o
70
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF3048BVX25WV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 8 DMA Controller
Table 8.8
Register
Legend:
MAR: Memory address register
IOAR: I/O address register
ETCR: Execute transfer count register
In repeat mode ETCRH is used as the transfer counter while ETCRL holds the initial transfer
count. ETCRH is decremented by 1 at each transfer until it reaches H'00, then is reloaded from
ETCRL. MAR is also restored to its initial value, which is calculated from the DTSZ and DTID
bits in DTCR. Specifically, MAR is restored as follows:
ETCRH and ETCRL should be initially set to the same value.
In repeat mode transfers continue until the CPU clears the DTE bit to 0. After DTE is cleared to 0,
if the CPU sets DTE to 1 again, transfers resume from the state at which DTE was cleared. No
CPU interrupt is requested.
Rev. 3.00 Sep 27, 2006 page 228 of 872
REJ09B0325-0300
23
23
All 1s
MAR
MAR
Register Functions in Repeat Mode
MAR – (–1)
7
7
ETCRH
7
ETCRL
IOAR
0
0
0
0
DTID
Activated by
SCI0 Receive-
Data-Full
Interrupt
Destination
address
register
Source
address
register
Transfer
counter
Initial transfer
count
· 2
DTSZ
Function
· ETCRL
Other
Activation
Source
address
register
Destination
address
register
Transfer
counter
Initial transfer
count
Initial Setting
Destination or
source address
Source or
destination
address
Number of
transfers
Number of
transfers
Operation
Incremented or
decremented at
each transfer
until H'0000,
then restored to
initial value
Held fixed
Decremented
once per
transfer until
H'0000 is
reached, then
reloaded from
ETCRL
Held fixed
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