DF3048BVX25WV Renesas Electronics America, DF3048BVX25WV Datasheet - Page 636
![MCU 3/5V 128K PB-FREE 100-TQFP](/photos/28/61/286123/100-tqfp__100-vqfp_sml.jpg)
DF3048BVX25WV
Manufacturer Part Number
DF3048BVX25WV
Description
MCU 3/5V 128K PB-FREE 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Specifications of DF3048BVX25WV
Core Processor
H8/300H
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, PWM, WDT
Number Of I /o
70
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF3048BVX25WV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 18 ROM (H8/3048F-ONE: Single Power Supply, H8/3048B Mask ROM Version)
If erasing multiple blocks, set a single bit in EBR for the next block to be erased, and repeat the
erase/erase-verify sequence as before.
Rev. 3.00 Sep 27, 2006 page 608 of 872
REJ09B0325-0300
Notes: 1. Prewriting (setting erase block data to all 0s) is not necessary.
2. Verify data is read in 16-bit (word) units.
3. Make only a single-bit specification in the erase block register (EBR). Two or more bits must not be set simultaneously.
4. Erasing is performed in block units. To erase multiple blocks, each block must be erased in turn.
5. The wait times and the value of N are shown in section 21.1.6, Flash Memory Characteristics.
Figure 18.14 Erase/Erase-Verify Flowchart (Single-Block Erasing)
Increment
address
No
Set block start address as verify address
H'FF dummy write to verify address
Clear ESU bit in FLMCR1
Clear SWE bit in FLMCR1
Set SWE bit in FLMCR1
Set ESU bit in FLMCR1
Clear EV bit in FLMCR1
Clear E bit in FLMCR1
Set EV bit in FLMCR1
Last address of block?
Set E bit in FLMCR1
Verify data = all 1s?
Read verify data
End of erasing
Wait (t
Wait (t
Wait (t
Wait (t
Wait (t
Disable WDT
Wait (t
Wait (t
Enable WDT
Wait (t
Wait (t
Set EBR
n = 1
Start
sswe
cswe
sesu
cesu
sevr
sev
cev
se
ce
Yes
Yes
) ms
) s
) s
) s
) s
) s
) s
) s
) s
*
1
No
*
*
*
Start of erase
*
Erase halted
*
*
*
*
*
*
*
5
3,
5
5
5
5
5
5
2
5
5
*
4
Perform erasing in block units.
Clear SWE bit in FLMCR1
Clear EV bit in FLMCR1
Wait (t
Wait (t
Erase failure
n
cswe
cev
N?
Yes
) s
) s
*
5
No
n
*
*
5
5
n + 1
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