DF3048BVX25WV Renesas Electronics America, DF3048BVX25WV Datasheet - Page 895

• Manufacturer Part Number: DF3048BVX25WV
• Description: MCU 3/5V 128K PB-FREE 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of DF3048BVX25WV

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Reset in T3 State
Figure D.3 is a timing diagram for the case in which RES goes low during the T3 state of an
external memory access cycle. As soon as RES goes low, all ports are initialized to the input state.
AS, RD, HWR, and LWR go high, and the data bus goes to the high-impedance state. The address
bus outputs are held during the T3 state.The same timing applies when a reset occurs in the T2
state of an access cycle to a two-state-access area.
RES
Internal
reset signal
Address bus
CS
CS
AS
RD (read access)
HWR, LWR
(write access)
Data bus
(write access)
I/O port
0
7
to CS
Figure D.3 Reset during Memory Access (Reset during T3 State)
1
Access to external address
T1
T2
Rev. 3.00 Sep 27, 2006 page 867 of 872
T3
Appendix D Pin States
High-impedance
High-impedance
High-impedance
H'000000
REJ09B0325-0300